Inventor

CHEN CHIEN HAO

TW157 patents

⚠️ This page may combine multiple inventors who share the name “CHEN CHIEN HAO”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

CHEN CHIEN HAO

TAIWAN SEMICONDUCTOR MFG

Process for integration of a high dielectric constant gate insulator layer in a CMOS device

Semiconductor device and method of making the same

Method for selectively stressing MOSFETs to improve charge carrier mobility

Integrated high-K/metal gate in CMOS process flow

Super anneal for process induced strain modulation

Strained transistor with hybrid-strain inducing layer

Method of forming plasma nitrided gate dielectric layers

Method to neutralize fixed charges in high K dielectric

Method for forming metal gates in a gate last process

Method of forming a locally strained transistor

Method for forming integrated advanced semiconductor device using sacrificial stress layer

Selective nitride liner formation for shallow trench isolation

Method of forming SOI-like structure in a bulk semiconductor substrate using self-organized atomic migration

Method of generating multiple oxides by plasma nitridation on oxide

Method of forming a silicon nitride-silicon dioxide gate stack

Method of generating multiple oxides by plasma nitridation on oxide

Integrated high-k/metal gate in CMOS process flow

Method of integrating high-K/metal gate in CMOS process flow

Junction leakage reduction in SiGe process by implantation

Profile confinement to improve transistor performance

Method of making MOSFET device with localized stressor

Method of generating multiple oxides by plasma nitridation on oxide

Process for integration of a high dielectric constant gate insulator layer in a CMOS device

Selective nitride liner formation for shallow trench isolation

TAIWAN SEMICONDUCTOR MFG CO LTD

Field effect transistor contact with reduced contact resistance

Integrated high-K/metal gate in CMOS process flow

Post UV cure for gapfill improvement

Semiconductor structure and method for forming the same

Semiconductor device and method of manufacture

Selective hybrid capping layer for metal gates of transistors

Gate resistance reduction through low-resistivity conductive layer

Gap-filling germanium through selective bottom-up growth

Field effect transistor contact with reduced contact resistance

Cap layer and anneal for gapfill improvement

Field effect transistor contact with reduced contact resistance

Self-aligned multiple spacer patterning process

Selective silicon growth for gapfill improvement

CHEN CHIEN HAO

Illumination fan connectable with at least one illumination fan for a computer

Graphics card lifting device

Luminous wire

LIAO CHIN-I

Multi-gate field-effect transistor and process thereof

Semiconductor process

UNITED MICROELECTRONICS CORP

Semiconductor device having a metal gate and fabricating method thereof

Method for forming semiconductor structure having TiN layer

CHEN CHIEN-HAO

Method of fabricating a sealing structure for high-k metal gate

Sealing structure for high-K metal gate

HOU YONG-TIAN

Integrated circuit metal gate structure and method of fabrication

TSAI MIN-CHUAN

Semiconductor structure and process thereof

YANG JI-YI

Method of forming SOI-like structure in a bulk semiconductor substrate by annealing a lower portion of a trench while protecting an upper portion of the trench

TSAI MING-CHIEH

Illuminated touch sensitive surface module and illuminated device thereof