Profile confinement to improve transistor performance

Abstract

A semiconductor device having well-defined profiles is disclosed. A p-type pocket/halo region is preferably formed along a channel-side border of the heavily doped source/drain region to neutralize diffused n-type elements. A diffusion-retarding region is formed to retard diffusion for both p-type and n-type impurities by substantially overlapping or extending beyond the p-type pocket/halo region and the N+ S/D region at least on the channel side.

1. A semiconductor device comprising:
 a semiconductor substrate with a channel region; 
 a gate dielectric over the channel region; 
 a gate electrode over the gate dielectric; 
 a lightly doped source/drain (LDD) region substantially aligned with an edge of the gate electrode, the LDD region comprising an n-type impurity; 
 a heavily doped source/drain (N+ S/D) region in the semiconductor substrate, the N+ S/D region comprising an n-type impurity and being further away from the channel region than the LDD region; 
 a p-type pocket/halo region substantially along a border of the N+ S/D region, the border being on a side close to the channel region; and 
 a diffusion-retarding region in the semiconductor substrate substantially aligned with an edge of the gate electrode, wherein the diffusion-retarding region comprises fluorine, and wherein the diffusion-retarding region is substantially deeper than the N+ S/D region, and wherein the diffusion-retarding region extends into a region underlying the gate electrode. 
 
   
   
     2. The semiconductor device of  claim 1  wherein the diffusion-retarding region further comprises a material selected from the group consisting essentially of carbon, nitrogen, and combinations thereof. 
   
   
     3. The semiconductor device of  claim 1  wherein the diffusion-retarding region is substantially deeper than the p-type pocket/halo region. 
   
   
     4. The semiconductor device of  claim 1  wherein the diffusion-retarding region has a side border substantially closer to the channel region than the p-type pocket/halo region. 
   
   
     5. The semiconductor device of  claim 1  wherein the diffusion-retarding region is substantially deeper than the LDD region. 
   
   
     6. The semiconductor device of  claim 1  wherein the diffusion-retarding region has a side border substantially closer to the channel region than the LDD region. 
   
   
     7. The semiconductor device of  claim 1  wherein the p-type pocket/halo comprises a material selected from the group consisting essentially of boron, BF2, indium, and combinations thereof. 
   
   
     8. The semiconductor device of  claim 1  wherein the LDD region and the N+ S/D region comprise a material selected from the group consisting essentially of arsenic, phosphorus, and combinations thereof. 
   
   
     9. The semiconductor device of  claim 1  wherein the pocket/halo region is located substantially along a bottom border of the N+ S/D region. 
   
   
     10. The semiconductor device of  claim 1  wherein the gate electrode comprises a diffusion-retarding material and an n-type impurity. 
   
   
     11. A device comprising:
 a substrate; 
 a diffusion-retarding region in the substrate, wherein the diffusion-retarding region comprises fluorine; 
 a source/drain region of a first conductivity type in the substrate and substantially contained within the diffusion-retarding region; and 
 a pocket/halo region of an opposite conductivity type formed substantially adjacent an interface of the source/drain region and the substrate, the pocket/halo region being substantially contained within the diffusion-retarding region. 
 
   
   
     12. The device of  claim 11  wherein the first conductivity type is n-type. 
   
   
     13. The device of  claim 11  wherein the source/drain region further comprises a LDD region and a heavily doped region. 
   
   
     14. The device of  claim 11  wherein the diffusion-retarding region further comprises a material selected from the group consisting essentially of carbon, nitrogen, and combinations thereof. 
   
   
     15. A semiconductor device comprising:
 a semiconductor substrate with a channel region; 
 a gate dielectric over the channel region; 
 a gate electrode over the gate dielectric; 
 a lightly doped source/drain (LDD) region substantially aligned with an edge of the gate electrode, the LDD region comprising an n-type impurity; 
 a heavily doped source/drain (N+ S/D) region in the semiconductor substrate, the N+ S/D region comprising an n-type impurity and being further away from the channel region than the LDD region; 
 a p-type pocket/halo region substantially along a border of the N+ S/D) region, the border being on a side close to the channel region; and 
 a diffusion-retarding region in the semiconductor substrate substantially aligned with an edge of the gate electrode, wherein the diffusion-retarding region comprises fluorine, and wherein the pocket/halo region is located substantially along a bottom border of the N+ S/D region.