Inventor

NIEH CHUN-FENG

TW82 patents

⚠️ This page may combine multiple inventors who share the name “NIEH CHUN-FENG”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

NIEH CHUN-FENG

TAIWAN SEMICONDUCTOR MFG CO LTD

Enhanced channel strain to reduce contact resistance in NMOS FET devices

Enhanced channel strain to reduce contact resistance in NMOS FET devices

Semiconductor device and method of manufacture

finFET device and methods of forming

Enhanced channel strain to reduce contact resistance in NMOS FET devices

Method of manufacturing semiconductor devices

Method of manufacturing semiconductor device

Fabrication of ultra-shallow junctions

Method of manufacturing semiconductor devices

Ion implantation for nano-FET

Semiconductor device with implant and method of manufacturing same

FinFET device and methods of forming

Gate structure of semiconductor device and method of manufacture

Ion implantation for nano-FET

Enhanced channel strain to reduce contact resistance in NMOS FET devices

FinFET device and methods of forming

Semiconductor device and method of making

Method for fabricating a semiconductor device

Method for fabricating a semiconductor device

Semiconductor structure and method for manufacturing the same

Reduce well dopant loss in FinFETs through co-implantation

Gradient doped region of recessed fin forming a FinFET device

Ion implantation of nanostructures for nano-FET

Gate structure of semiconductor device and method of manufacture

Semiconductor device with implant and method of manufacturing same

Enhanced channel strain to reduce contact resistance in NMOS FET devices

Semiconductor device and manufacturing method thereof

Dual dopant source/drain regions and methods of forming same

Method for fabricating a semiconductor device

Implantation and annealing for semiconductor device

Enhanced channel strain to reduce contact resistance in NMOS FET devices

Semiconductor device and manufacturing method thereof

Semiconductor device with implant and method of manufacturing same

TAIWAN SEMICONDUCTOR MFG

Method of making a FinFET device

Super anneal for process induced strain modulation

Source/drain carbon implant and RTA anneal, pre-SiGe deposition

Semiconductor device and method of making

Junction leakage reduction in SiGe process by implantation

Formation of high quality fin in 3D structure by way of two-step implantation

Profile confinement to improve transistor performance

Method for improving selectivity of epi process

Method of manufacturing strained source/drain structures

Shallow junction formation and high dopant activation rate of MOS devices

Short channel effect engineering in MOS device using epitaxially carbon-doped silicon

NIEH CHUN-FENG

Method of manufacturing strained source/drain structures

Forming a protective film on a back side of a silicon wafer in a III-V family fabrication process

WOON WEI-YEN

Source/drain carbon implant and RTA anneal, pre-SiGe deposition

CHEN KUAN-YU

Method for improving selectivity of epi process

LIN HUNG-TA

III-V multi-channel FinFETs

SU YU-CHEN

Methods for introducing carbon to a semiconductor structure