Ion implantation for nano-FET

Abstract

A nanoFET transistor includes doped channel junctions at either end of a channel region for one or more nanosheets of the nanoFET transistor. The channel junctions are formed by a iterative recessing and implanting process which is performed as recesses are made for the source/drain regions. The implanted doped channel junctions can be controlled to achieve a desired lateral straggling of the doped channel junctions.

What is claimed is: 
     
       1. A device comprising:
 a first nanostructure, the first nanostructure comprising a first doped channel junction at either end; 
 a second nanostructure over the first nanostructure, the second nanostructure comprising a second doped channel junction at either end; 
 a gate structure disposed over the first nanostructure and the second nanostructure, the gate structure extending between the first nanostructure and the second nanostructure; 
 a source/drain region adjacent the gate structure, the source/drain region contacting the first nanostructure and the second nanostructure; and 
 an inner spacer disposed at either end of the first nanostructure, the inner spacer extending between the first nanostructure and the second nanostructure, the inner spacer interposed between a gate dielectric of the gate structure and the source/drain region, the inner spacer comprising a first dopant, a peak concentration of the first dopant at an interface of the inner spacer and the gate dielectric. 
 
     
     
       2. The device of  claim 1 , wherein the first doped channel junction has a first lateral straggling between 3 nm and 5 nm. 
     
     
       3. The device of  claim 2 , wherein the second doped channel junction has a second lateral straggling which is different than the first lateral straggling. 
     
     
       4. The device of  claim 1 , wherein a first concentration of dopant in the first doped channel junction is between 1×10 18  cm −3  and 1×10 22  cm −3 . 
     
     
       5. The device of  claim 1 , further comprising:
 a first channel length between the first doped channel junction at one end of the first nanostructure and a doped channel junction at an opposite end of the first nanostructure; and 
 a second channel length between the second doped channel junction at one end of the second nanostructure and a doped channel junction at an opposite end of the second nanostructure, wherein the second channel length is different than the first channel length. 
 
     
     
       6. The device of  claim 1 , wherein the first doped channel junction has a first lateral straggling, wherein the second doped channel junction has a second lateral straggling, wherein the first lateral straggling is different than the second lateral straggling. 
     
     
       7. A transistor comprising:
 a first nanostructure, the first nanostructure comprising first doped channel junctions at each end and a first undoped channel length between the first doped channel junctions; 
 a second nanostructure over the first nanostructure, the second nanostructure comprising second doped channel junctions at each end and a second undoped channel length between the second doped channel junctions, wherein the first undoped channel length is a different value than the second undoped channel length; 
 a gate structure disposed over the first nanostructure and the second nanostructure, the gate structure extending between the first nanostructure and the second nanostructure; and 
 a source/drain region adjacent the gate structure, the source/drain region contacting the first nanostructure and the second nanostructure. 
 
     
     
       8. The transistor of  claim 7 , further comprising a third nanostructure over the second nanostructure, the gate structure extending between the second nanostructure and the third nanostructure, wherein the third nanostructure comprises third doped channel junctions at each end and a third undoped channel length between the third doped channel junctions. 
     
     
       9. The transistor of  claim 8 , wherein at least two of the first undoped channel length, the second undoped channel length, and the third undoped channel length are different values. 
     
     
       10. The transistor of  claim 9 , wherein the first undoped channel length, the second undoped channel length, and the third undoped channel length are all different values. 
     
     
       11. The transistor of  claim 7 , further comprising a first inner spacer interposed between the first nanostructure and the second nanostructure and interposed between the gate structure and the source/drain region, the first inner spacer comprising an insulating material and a first dopant. 
     
     
       12. The transistor of  claim 11 , wherein a concentration of the first dopant in the first inner spacer is greatest adjacent to the gate structure. 
     
     
       13. A method comprising:
 forming multiple nanostructures over a substrate; 
 forming a gate structure over the multiple nanostructures; 
 performing a first angled ion implantation to implant first dopants into a first channel end of a first nanostructure of the multiple nanostructures, the first channel end under the gate structure; 
 etching the first nanostructure of the multiple nanostructures to form a first recess in the first nanostructure adjacent the gate structure, the etching exposing the first channel end of the first nanostructure; 
 performing a second angled ion implantation to implant second dopants into a second channel end of a second nanostructure, the second channel end under the gate structure; 
 etching the second nanostructure of the multiple nanostructures to extend the first recess and form a second recess in the second nano structure adjacent the gate structure, the etching exposing the second channel end of the second nanostructure; 
 etching to extend the second recess to form a third recess over the substrate; and 
 depositing a source/drain region in the third recess. 
 
     
     
       14. The method of  claim 13 , further comprising:
 recessing sidewalls of a third nanostructure of the multiple nanostructures disposed between the first nanostructure and the second nanostructure; and 
 depositing an inner spacer on the sidewalls of the third nanostructure. 
 
     
     
       15. The method of  claim 14 , wherein the sidewalls of the third nanostructure comprise implanted ions from the first angled ion implantation or the second angled ion implantation, further comprising annealing the third nanostructure and inner spacer, the annealing diffusing implanted ions from the third nanostructure to the inner spacer. 
     
     
       16. The method of  claim 14 , wherein the first angled ion implantation implants first dopants a first lateral distance into the first channel end of the first nanostructure, and wherein the second angled ion implantation implants second dopants a second lateral distance into the second channel end of the second nanostructure. 
     
     
       17. The method of  claim 16 , wherein the first lateral distance and the second lateral distance have different values. 
     
     
       18. The method of  claim 16 , wherein the first lateral distance and the second lateral distance are each between 3 nm and 5 nm. 
     
     
       19. The method of  claim 13 , further comprising: after etching the first nanostructure to form the first recess, performing a surface clean of the first recess. 
     
     
       20. The method of  claim 13 , wherein the first dopants are a different species than the second dopants.