Enhanced channel strain to reduce contact resistance in NMOS FET devices

Abstract

A semiconductor device includes a substrate, a fin structure and an isolation layer formed on the substrate and adjacent to the fin structure. The semiconductor device includes a gate structure formed on at least a portion of the fin structure and the isolation layer. The semiconductor device includes an epitaxial layer including a strained material that provides stress to a channel region of the fin structure. The epitaxial layer has a first region and a second region, in which the first region has a first doping concentration of a first doping agent and the second region has a second doping concentration of a second doping agent. The first doping concentration is greater than the second doping concentration. The epitaxial layer is doped by ion implantation using phosphorous dimer.

What is claimed is: 
     
       1. A semiconductor device, comprising:
 one or more n-type Fin FET structures; and 
 one or more p-type Fin FET structures, 
 wherein the n-type Fin FET structure comprises: 
 a first gate structure formed over a channel region of a first fin structure; and 
 first source/drain regions formed on the first fin structure on opposing sides of the first gate structure; and 
 wherein the first source/drain regions have a first region and a second region, the first region being located closer to a surface of the first source/drain regions, 
 the first region has a first dopant and the second region has a second dopant, and 
 the first region has a first doping concentration of the first dopant of greater than 1×10 22  atoms/cm 3 . 
 
     
     
       2. The semiconductor device of  claim 1 , wherein the first dopant is a phosphorous dimer dopant and the second dopant is a phosphorous dopant. 
     
     
       3. The semiconductor device of  claim 1 , wherein the first source/drain regions comprise SiGe. 
     
     
       4. The semiconductor device of  claim 1 , wherein the p-type Fin FET structure includes second source/drain regions, and the second source/drain regions comprise SiP or SiC. 
     
     
       5. The semiconductor device of  claim 1 , wherein the p-type Fin FET structures include a first fin structure having a channel region and a second fin structure having a channel region, and
 the channel region of the first fin structure has a higher channel mobility than the channel region of the second fin structure. 
 
     
     
       6. The semiconductor device of  claim 1 , wherein a doping concentration of the second dopant is in a range from 1×10 15  atoms/cm 3  to 4×10 15  atoms/cm 3 . 
     
     
       7. The semiconductor device of  claim 1 , wherein the first dopant is disposed over a top surface of the second region. 
     
     
       8. A semiconductor device, comprising:
 one or more p-type Fin FET structures, 
 wherein the p-type Fin FET structure comprises a first gate structure formed over a channel region of a first fin structure; 
 one or more n-type Fin FET structures, 
 wherein the n-type Fin FET structure comprises: 
 a second gate structure formed over a channel region of a second fin structure; and 
 first source/drain regions formed on the second fin structure on opposing sides of the second gate structure; and 
 wherein the first source/drain regions have a first region and a second region, the first region being located closer to a surface of the first source/drain regions, 
 the first region has a first dopant and the second region has a second dopant, 
 wherein the channel region of the second fin structure has a higher channel mobility than the channel region of the first fin structure, and 
 wherein the first dopant is a phosphorous dimer dopant and the second dopant is a phosphorous dopant. 
 
     
     
       9. The semiconductor device of  claim 8 , wherein the first source/drain regions comprise SiGe. 
     
     
       10. The semiconductor device of  claim 8 , wherein the p-type Fin FET structures include second source/drain regions, and the second source/drain structures comprise SiP or SiC. 
     
     
       11. The semiconductor device of  claim 8 , wherein the p-type Fin FET structures include a first fin structure having a channel region and a second fin structure having a channel region, and
 the channel region of the first fin structure has a higher channel mobility than the channel region of the second fin structure. 
 
     
     
       12. The semiconductor device of  claim 8 , wherein a doping concentration of the second dopant is in a range from 1×10 15  atoms/cm 3  to 4×10 15  atoms/cm 3 . 
     
     
       13. The semiconductor device of  claim 8 , wherein the first dopant is disposed over a top surface of the second region. 
     
     
       14. A semiconductor device, comprising:
 one or more n-type Fin FET structures; and 
 one or more p-type Fin FET structures, 
 wherein the n-type Fin FET structure comprises: 
 a first gate structure formed over a channel region of a first fin structure; and 
 first source/drain regions formed on the first fin structure on opposing sides of the first gate structure; and 
 wherein the first source/drain regions have a first region and a second region, the first region being located closer to a surface of the first source/drain regions, 
 the first region has a first dopant and the second region has a second dopant, and 
 the first region has a first doping concentration of the first dopant and the second region has a second doping concentration of the second dopant, 
 the first doping concentration is greater than the second doping concentration, and 
 a thickness of the first region from a surface of the first source/drain regions to the second region ranges from 0.1 nm to 8 nm. 
 
     
     
       15. The semiconductor device of  claim 14 , wherein the first dopant is a phosphorous dimer dopant and the second dopant is a phosphorous dopant. 
     
     
       16. The semiconductor device of  claim 14 , wherein the first source/drain regions comprise SiGe. 
     
     
       17. The semiconductor device of  claim 14 , wherein the p-type Fin FET structures include second source/drain regions, and the second source/drain structures comprise SiP or SiC. 
     
     
       18. The semiconductor device of  claim 14 , wherein the p-type Fin FET structures include a first fin structure having a channel region and a second fin structure having a channel region, and
 the channel region of the first fin structure has a higher channel mobility than the channel region of the second fin structure. 
 
     
     
       19. The semiconductor device of  claim 14 , wherein the first doping concentration of the first dopant is greater than 1×10 22  atoms/cm 3 . 
     
     
       20. The semiconductor device of  claim 14 , wherein a doping concentration of the second dopant is in a range from 1×10 15  atoms/cm 3  to 4×10 15  atoms/cm 3 .