Inventor

LIAW ING-RUEY

TW33 patents

⚠️ This page may combine multiple inventors who share the name “LIAW ING-RUEY”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

LIAW ING-RUEY

VANGUARD INT SEMICONDUCT CORP

Method for fabricating high density integrated circuits using oxide and polysilicon spacers

Methods of manufacture of crown or stack capacitor with a monolithic fin structure made with a different oxide etching rate in hydrogen fluoride vapor

Method for fabricating capacitor-over-bit-line dynamic random access memory (DRAM) using self-aligned contact etching technology

Method for fabricating a multiple walled crown capacitor of a semiconductor device

Method for forming interconnections and conductors for high density integrated circuits

Plasma-enhanced chemical vapor deposited SIO2 /SI3 N4 multilayer passivation layer for semiconductor applications

Method for crown type capacitor in dynamic random access memory

Method for making a plasma-enhanced chemical vapor deposited SiO2 Si3 N4 multilayer passivation layer for semiconductor applications

LDD spacers in MOS devices with double spacers

Method of fabricating LDD spacers in MOS devices with double spacers and device manufactured thereby

Crown or stack capacitor with a monolithic fin structure

Method for fabricating crown-shaped capacitor structures

Design and a novel process for formation of DRAM bit line and capacitor node contacts

Design and a novel process for formation of DRAM bit line and capacitor node contacts

Manufacture of a shallow trench isolation device by exposing negative photoresist to increased exposure energy and chemical mechanical planarization

Method for fabricating crown capacitors for a dram cell

Shallow trench isolator via non-critical chemical mechanical polishing

Method for fabricating a low resistance Poly-Si/metal gate

Method for forming a capacitor using a silicon oxynitride etching stop layer

Method for simultaneous formation of contacts between metal layers and fuse windows in semiconductor manufacturing

Method of manufacture of a crown or stack capacitor with a monolithic fin structure made with a different oxide etching rate in hydrogen fluoride vapor

Tungsten bit line structure featuring a sandwich capping layer

Method of forming landing plugs for PMOS and NMOS

Fabrication method to approach the conducting structure of a DRAM cell with straightforward bit line

Method of making greek letter psi shaped capacitor for DRAM circuits

Method for making polycide-to-polycide low contact resistance contacts for interconnections on integrated circuits

Method for making polycide-to-polycide low contact resistance contacts for interconnections on integrated circuits

Method for forming a polysilicon spacer with a vertical profile

Fabrication method for flash memory source line and flash memory

IND TECH RES INST

Small contacts for ultra large scale integration semiconductor devices without separation ground rule

Process of making an integrated circuit having a planar conductive layer

Method for fabricating DRAM cells having fin-type stacked storage capacitors

TAIWAN IMAGINGTEK CORP

Semiconductor ROM device and manufacturing method thereof