Method for fabricating crown capacitors for a dram cell

Abstract

A method is provided for fabricating a single crown electrode for a capacitor for semiconductor memory devices. A conductive layer is formed over a multi-layer gate and insulation structure. The conductive layer includes a portion extending through a contact hole to thereby electrically connect the conductive layer with an active region of a transistor formed in the substrate Next, a novel groove is etched in the conductive layer between adjacent memory cells. Sidewall spacers are formed on the groove. The conductive layer is anisotropically etched using the spacers as an etching mask, thereby forming a plurality of electrodes having upright portions. The etching exposes the first insulation layer in the area under the grooves, but leaves a thickness of the base conductive layer to form the bottom of the electrode. The spacers then are removed and a conformal dielectric layer is formed over the surface. Lastly, a top plate electrode is formed over the conformal dielectric layer.

What is claimed is: 
     
       1. A method of fabricating a crown capacitor for semiconductor memory devices, said memory devices having a field effect transistor including a source, a drain, and a gate element, and a first insulation layer over said field effect transistor, which comprises the steps of: forming a base conductive layer over said first insulation layer;   forming a contact hole through said base conductive layer and said first insulating layer over source regions that exposes said source;   forming a first conductive layer over said base conductive layer and filling said contact hole thereby forming an electrical connection to said source;   forming a first photoresist mask for defining areas for a plurality of spatially separated individual cell units on said first conductive layer;   etching portions of said first conductive layer through said first photoresist mask forming an groove in said first conductive layer between adjacent cells units, said groove having vertical sidewalls and having a depth less than   a thickness of said first conductive layer;   removing said first photoresist mask;   forming first spacers on said sidewalls of said groove;   anisotropically etching said base conductive layer and said first conductive layer using said spacers as an etch mask, thereby forming a plurality of electrodes having upright extending portions, said anisotropic etching exposing said first insulation layer in an area under said groove but leaving a thickness of said base conductive layer in the areas of said individual cell units and isotropically etching said exposed first insulating layer under said groove using said plurality of said electrodes as an etch mask;   removing said spacers;   forming a conformal dielectric layer covering at least said electrodes, said base conductive layer, and said first insulation layer; and   forming a top plate electrode over said conformal dielectric layer thereby forming a crown capacitor.   
     
     
       2. The method of claim 1 which further includes, after forming said base conductive layer, forming an opening having sidewalls through said base conductive layer and through a portion of said first insulation layer, forming polysilicon spacers on the sidewalls of said opening and using said spacers as an etch mask to form said contact hole. 
     
     
       3. The method of claim 1 where said base conductive layer has a thickness in a range between about 2000 and 4000 Angstroms and said base conductive layer is formed of polysilicon. 
     
     
       4. The method of claim 1 wherein said base conductive layer has a dopant concentration in a range of between about 1E20 and 1E 22 atoms/cm 3 . 
     
     
       5. The method of claim 1 wherein said first conductive layer has a thickness in a range between about 4000 and 12000 Angstroms and said first conductive layer is formed of polysilicon. 
     
     
       6. The method of claim 1 wherein said first conductive layer has a dopant concentration in a range of between about 1E20 and 1E22 atoms/cm 3 . 
     
     
       7. The method of claim 1 wherein the thickness (t1) of said base conductive layer after said anisotropically etching is in a range between about 500 and 2000 Angstroms and said groove has a depth in a range between about 500 and 2000 Angstroms. 
     
     
       8. The method of claim 1 wherein said first spacers have a width in a range between about 0.1 and 0.2 um and said first spacers are formed a material selected from the group consisting of silicon nitride and silicon oxide. 
     
     
       9. The method of claim 1 wherein said conformal dielectric layer has a thickness in a range between about 45 and 60 Anstroms and is formed of a material selected from the group consisting of silicon oxide, silicon nitride, and Ta 2  O 5 . 
     
     
       10. The method of claim 1 wherein said top plate electrode has a thickness in a range between about 1000 and 2000 Angstroms and can be formed of polysilicon. 
     
     
       11. A method of fabricating dynamic random access memory devices, said memory devices having a source, a drain, a gate element and a capacitor, which comprises the steps of: forming a first insulation layer over a substrate surface;   forming a base conductive layer over said first insulation layer;   forming a channel through said base conductive layer and through an upper portion of said first insulation layer, said channel having vertical sidewalls;   forming polysilicon sidewall spacers on said sidewalls of said channel;   forming a contact hole using said polysilicon sidewall spacers as an etch mask through at least said first insulating layer over source regions that exposes said source;   forming a first conductive layer over said base conductive layer and filling said contact hole thereby forming an electrical contact to said source;   forming a first photoresist mask for defining areas for a plurality of spatially separated individual cell units on said first conductive layer;   etching portions of said first conductive layer through said first photoresist mask forming an groove in said first conductive layer between adjacent cell units, said groove having vertical sidewalls and having a depth less than a thickness of said first conductive layer;   removing said first photoresist mask;   forming first spacers on said sidewalls of said groove;   anisotropically etching said base conductive layer and said first conductive layer using said first spacers as an etching mask, thereby forming a plurality of electrodes having upright extending portions, said anisotropic etching exposing said first insulation layer in an area under said groove, but leaving a thickness of said base conductive layer in the areas of said individual cell units;   removing said first spacers;   forming a conformal dielectric layer covering said electrodes, said base conductive layer, and said first insulation layer; and   forming a top plate electrode over said conformal dielectric layer which connects said top plate electrode of adjacent capacitors thus forming random access memory devices.   
     
     
       12. The method of claim 11 where said base conductive layer has a thickness in a range between about 2000 and 4000 Angstroms, said base conductive layer is formed of polysilicon, and said base conductive layer has a dopant concentration in a range of between about 1E20 and 1E 22 atoms/cm 3 . 
     
     
       13. The method of claim 11 wherein said first conductive layer has a thickness in a range between about 4000 and 12000 Angstroms and said first conductive layer has a dopant concentration in a range of between about 1E20 and 1E22 atoms/cm 3 . 
     
     
       14. The method of claim 11 wherein said first spacers have a width in a range between about 0.1 and 0.2 um and said first spacers are formed a material selected from the group consisting of silicon nitride and silicon oxide. 
     
     
       15. The method of claim 11 wherein said conformal dielectric layer has a thickness in a range between about 45 and 60 Angstroms and is formed of a material selected from the group consisting of silicon oxide, silicon nitride and Ta 2  O 5 . 
     
     
       16. The method of claim 11 wherein said top plate electrode has a thickness in a range between about 1000 and 2000 Angstroms and is formed of polysilicon. 
     
     
       17. A method of fabricating dynamic random access memory devices, said memory devices having a source, a drain, a gate element and a capacitor, which comprises the steps of: forming a first insulation layer over a substrate surface;   forming a base conductive layer over said first insulation layer;   forming a channel through said base conductive layer and through an upper portion of said first insulation layer, said channel having vertical sidewalls;   forming polysilicon sidewall spacers on said sidewalls of said channel;   forming a contact hole using said polysilicon sidewall spacers as an etch mask through at least said first insulating layer over source regions that exposes said source;   forming a first conductive layer over said base conductive layer and filling said contact hole thereby forming an electrical contact to said source;   forming a first photoresist mask for defining areas for a plurality of spatially separated individual cell units on said first conductive layer;   etching portions of said first conductive layer through said first photoresist mask forming a groove in said first conductive layer between adjacent cell units, said groove having vertical sidewalls and having a depth less than a thickness of said first conductive layer;   removing said first photoresist mask;   forming first spacers on said sidewalls of said groove;   anisotropically etching said base conductive layer and said first conductive layer using said first spacers as an etching mask, thereby forming a plurality of electrodes having upright extending portions, said anisotropic etching exposing said first insulation layer in an area under said groove, but leaving a thickness of said base conductive layer in the areas of said individual cell units;   isotropically etching said exposed first insulation layer under said groove using said plurality of said electrodes as an etch mask;   removing said first spacers;   forming a conformal dielectric layer covering said electrodes, said base conductive layer, and said first insulation layer; and   forming a top plate electrode over said conformal dielectric layer which connects said top plate electrode of adjacent capacitors thus forming random access memory devices.   
     
     
       18. The method of claim 17 wherein said first conductive layer has a thickness in a range between about 4000 to 12000 Angstroms. 
     
     
       19. The method of claim 17 wherein said first conductive layer has a dopant concentration in a range of between about 1E20 and 1E22 atoms/cm 3 . 
     
     
       20. The method of claim 17 wherein said groove has a depth in a range between about 500 and 2000 Angstroms. 
     
     
       21. The method of claim 17 wherein said first spacers have a width in a range between about 0.1 and 0.2 um and said first spacers are formed of a material selected from the group consisting of silicon nitride and silicon oxide. 
     
     
       22. The method of claim 17 wherein said conformal dielectric layer has a thickness in a range between about 45 and 60 Angstroms and is formed of a material selected from the group consisting of silicon oxide, silicon nitride, and Ta 2  O 5 .