Inventor

MEHRAD FREIDOON

US53 patents

⚠️ This page may combine multiple inventors who share the name “MEHRAD FREIDOON”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

MEHRAD FREIDOON

TEXAS INSTRUMENTS INC

Integration of pre-S/D anneal selective nitride/oxide composite cap for improving transistor performance

Extended-life method for soft-programming floating-gate memory cells

Method of fabricating a source line in flash memory having STI structures

Non-volatile flash layout

Nonvolatile memory cell with P-N junction formed in polysilicon floating gate

Nonvolatile memory array with compatible vertical source lines

Channel-stop process for use with thick-field isolation regions in triple-well structures

Gate dielectric first replacement gate processes and integrated circuits therefrom

Method for moat nitride pull back for shallow trench isolation

Semiconductor device isolation structure and method of forming

Multi-layer silicide block process

Method to fabricate a semiconductor resistor in embedded flash memory application

Method to salicide source-line in flash memory with STI

Method to form an embedded flash memory circuit with reduced process steps

Method to reduce source-line resistance in flash memory with sti

Gate dielectric first replacement gate processes and integrated circuits therefrom

Method to design for or modulate the CMOS transistor threshold voltage using shallow trench isolation (STI)

Method for forming a bottom corner rounded STI

Source line fabrication process for flash memory

Multi-layer reducible sidewall process

Method and system for testing and adjusting threshold voltages in flash eeproms

Transistor formed from stacked disposable sidewall spacer

Flash memory array structure and method of forming

Stack etch method for flash memory devices

Shallow trench isolation structure and method

Implanted vertical source-line under straight stack for flash eprom

Selective wet etch process for CMOS ICs having embedded strain inducing regions and integrated circuits therefrom

Method of forming a silicided gate utilizing a CMP stack

Method of forming a fully silicided semiconductor device with independent gate and source/drain doping and related device

Shallow trench isolation step height detection method

Reducing gate CD bias in CMOS processing

Integration of pre-S/D anneal selective nitride/oxide composite cap for improving transistor performance

Method to obtain fully silicided poly gate

Method of simultaneously siliciding a polysilicon gate and source/drain of a semiconductor device, and related device

Method to obtain fully silicided gate electrodes

Method to improve STI nano gap fill and moat nitride pull back

Flash memory cell process using a hardmask

Flash memory cell process using a hardmask

Flash memory array structure and method of forming

Method to implant NMOS polycrystalline silicon in embedded FLASH memory applications

Process method to facilitate silicidation

Method to fabricate a self aligned source resistor in embedded flash memory applications

Sidewall process for forming a low resistance source line

Method for forming MOS transistors with improved sidewall structures

Process method to fully salicide (FUSI) both N-poly and P-poly on a CMOS flow

Method for forming CMOS transistors having FUSI gate electrodes and targeted work functions

Forming a trench to define one or more isolation regions in a semiconductor structure

Method to form shallow trench isolation with rounded upper corner for advanced semiconductor circuits

Method to form shallow trench isolation with rounded upper corner for advanced semiconductor circuits

MEHRAD FREIDOON

Method of forming fully silicided NMOS and PMOS semiconductor devices having independent polysilicon gate thicknesses, and related device