Nonvolatile memory cell with P-N junction formed in polysilicon floating gate

Abstract

An integrated circuit memory cell (10) is formed with a P-N junction polycrystalline floating gate (13) with a lightly boron doped on the source side (13B) and a heavily arsenic or phosphorous doped on the drain side (13A) plus the channel region (Ch) . The cells (10) are formed in an array at a face of a semiconductor body (22), each cell including a source (11) and including a drain (12). An improved over-erase characteristic is achieved by forming a P-N junction (JU) in the floating gate (13). Use of a P-N junction (JU) in polycrystalline floating gate (13) prevents the cell (10) from going into depletion, causes a tighter distribution of erased threshold voltages VT, and improves device life because fewer electrons travel through the gate oxide (30).

What is claimed is: 
     
       1. A memory cell of the type having a floating gate and a source underlying and insulated from said floating gate, said floating gate chargeable to control the conductivity of a channel adjacent said source, said floating gate comprising: a first polysilicon region of N-type conductivity;   a second polysilicon region of P-type conductivity;   a P-N junction at the intersection of said first polysilicon region and said second polysilicon region in said floating gate; and   said source underlying and insulated from said second polysilicon region of P-type conductivity.   
     
     
       2. The memory cell of claim 1, wherein said memory cell is erased using Fowler-Nordheim tunnelling. 
     
     
       3. The memory cell of claim 1, wherein said floating gate is programmed by channel-hot-electrons. 
     
     
       4. The memory cell of claim 1, wherein said first polysilicon region includes boron doping at a concentration of about 20×10 12  /cm 2  to 80×10 12  /cm 2 . 
     
     
       5. The memory cell of claim 1, wherein said second polysilicon region includes arsenic doping at a concentration level of about 20×10 13  /cm 2  to 80×10 13  /cm 2 . 
     
     
       6. The memory cell of claim 1, wherein said second polysilicon region includes phosphorus doping at a concentration level of 20×10 13  /cm 2  to 80×10 13  /cm 2 .