Inventor

JAIN SANJEEV KUMAR

CA53 patents

⚠️ This page may combine multiple inventors who share the name “JAIN SANJEEV KUMAR”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

JAIN SANJEEV KUMAR

TAIWAN SEMICONDUCTOR MFG CO LTD

Write driver boost circuit for memory cells

Systems and methods for controlling power management operations in a memory device

Systems and methods for controlling power management operations in a memory device

Systems and methods for controlling power management operations in a memory device

Systems and methods for controlling power assertion in a memory device

Write driver boost circuit for memory cells

Low power wake up for memory

Memory circuit including an array control inhibitor

Systems and methods for controlling power assertion in a memory device

Memory architecture

Level shifter

Memory array having disturb detector and write assistor

Bit line pre-charge circuit for power management modes in multi bank SRAM

Memory circuit and method of operating same

Bit line pre-charge circuit for power management modes in multi bank SRAM

Memory input hold time adjustment

Low power wake up for memory

Memory device, read clock generation circuit, and method for controlling read operation in memory device

Robust circuit for negative bit line generation in SRAM cells

Systems and methods for a power wake-up sequence in a memory device

Memory circuit including an array control inhibitor

Systems and methods for controlling power assertion in a memory device

Write driver boost circuit for memory cells

Circuitry for power management assertion

Memory circuit including an array control inhibitor

Low power scheme for power down in integrated dual rail SRAMs

Circuitry for power management assertion

Memory power management

Memory circuit and method of operating same

Bit line pre-charge circuit for power management modes in multi bank SRAM

Tracking circuitry and memory devices including the same

Systems and methods for improved data access speed

Memory device

Memory device and power management method using the same

Word line driver for low voltage operation

Dual rail SRAM device

Memory device and compensation method therein

Memory power management

FREESCALE SEMICONDUCTOR INC

Efficient word lines, bit line and precharge tracking in self-timed memory device

Low power read scheme for read only memory (ROM)

JOHN JOSHY

Axially-oriented cellular seal structure for turbine shrouds and related method

Vortex chambers for clearance flow control

GEN ELECTRIC

Rotor shaft cooling

Turbine disc assemblies and methods of fabricating the same

JAIN SANJEEV KUMAR

Efficient word lines, bit line and precharge tracking in self-timed memory device

Contoured honeycomb seal for a turbomachine

SYNOPSYS INC

Input trigger independent low leakage memory circuit

SUTHAR RAJNIKUMAR NANDALAL

Passive cooling system for a turbomachine

ST MICROELECTRONICS PVT LTD

Flip chip device having simplified routing

INDIAN INST OF TECH DELHI

QRS complex identification in electrocardiogram signals