Inventor
DECHENE DANIEL JAMES
US16 patents
Patents
16 patentsUS10998193B1May 4, 2021
Spacer-assisted lithographic double patterning
IBM2 citations72
US11515427B2Nov 29, 2022
Precise bottom junction formation for vertical transport field effect transistor with highly doped epitaxial source/drain, sharp junction gradient, and/or reduced parasitic capacitance
IBM4 citations71
US12575399B2Mar 10, 2026
Interconnect structure including vertically stacked power and ground lines
IBM0 citations62
US12400871B2Aug 26, 2025
Metal lines with low via-to-via spacing
IBM0 citations62
US12363965B2Jul 15, 2025
Stacked transistor layout for improved cell height scaling
IBM0 citations62
US11977614B2May 7, 2024
Circuit design watermarking
IBM0 citations62
US12080559B2Sep 3, 2024
Using a same mask for direct print and self-aligned double patterning of nanosheets
IBM0 citations61
US12068415B2Aug 20, 2024
Precise bottom junction formation for vertical transport field effect transistor with highly doped epitaxial source/drain, sharp junction gradient, and/or reduced parasitic capacitance
IBM0 citations61
US11888048B2Jan 30, 2024
Gate oxide for nanosheet transistor devices
IBM0 citations61
US11257681B2Feb 22, 2022
Using a same mask for direct print and self-aligned double patterning of nanosheets
IBM0 citations61
US11211474B2Dec 28, 2021
Gate oxide for nanosheet transistor devices
IBM0 citations61
US12550711B2Feb 10, 2026
Interconnection fabric for buried power distribution
IBM0 citations52
US11024551B1Jun 1, 2021
Metal replacement vertical interconnections for buried capacitance
IBM0 citations52
US11527434B2Dec 13, 2022
Line cut patterning using sacrificial material
IBM0 citations51
US11158536B2Oct 26, 2021
Patterning line cuts before line patterning using sacrificial fill material
IBM0 citations51
US11830778B2Nov 28, 2023
Back-side wafer modification
IBM0 citations50