Stacked transistor layout for improved cell height scaling

Abstract

Embodiments of the invention include a first source region and a first drain region forming a first L-shaped layout. The first source and drain regions are formed on a bottom gate spacer material. Embodiments include a second source region and a second drain region forming a second L-shaped layout, the first L-shaped layout and the second L-shaped layout being interrupted by a gate. One of the first source and drain regions extends in a direction beyond the bottom gate spacer material to form the first L-shaped layout, wherein the direction is parallel to a lengthwise direction of the gate.

What is claimed is: 
     
       1. A semiconductor structure comprising:
 a first source region and a first drain region forming a first L-shaped layout, the first source and drain regions being formed on a bottom gate spacer material; and 
 a second source region and a second drain region forming a second L-shaped layout, the first L-shaped layout and the second L-shaped layout being interrupted by a gate, wherein one of the first source and drain regions extends in a direction beyond the bottom gate spacer material to form the first L-shaped layout, wherein the direction is parallel to a lengthwise direction of the gate. 
 
     
     
       2. The semiconductor structure of  claim 1 , wherein:
 the first source region and the first drain region comprise epitaxial material; and 
 the second source region and the second drain region comprise epitaxial material. 
 
     
     
       3. The semiconductor structure of  claim 1 , wherein a stacked field-effect transistor comprises the first source region, the first drain region, the second source region, the second drain region, and the gate. 
     
     
       4. The semiconductor structure of  claim 1 , wherein a first portion of the first L-shaped layout overlaps a second portion of the second L-shaped layout. 
     
     
       5. The semiconductor structure of  claim 1 , wherein the first L-shaped layout and the second L-shaped layout have different orientations such that the first and second L-shaped layouts avoid a complete overlap. 
     
     
       6. The semiconductor structure of  claim 1 , wherein a first channel region associated with the first source region and the first drain region overlaps a second channel region associated with the second source region and the second drain region. 
     
     
       7. The semiconductor structure of  claim 1 , wherein the first source region and the first drain region are doped to be complementary to the second source region and the second drain region. 
     
     
       8. The semiconductor structure of  claim 1 , wherein a first end of the first L-shaped layout is configured to operatively couple to a first power source and a second end of the second L-shaped layout is configured to operatively couple to a second power source, the first end and the second end being non-overlapping. 
     
     
       9. The semiconductor structure of  claim 1 , wherein an overlapped end of the first L-shaped layout and the second L-shaped layout is configured to operatively couple to an output connection. 
     
     
       10. The semiconductor structure of  claim 1 , wherein the gate is configured to operatively coupled to an input connection in proximity to the first source and drain regions and the second source and drain regions. 
     
     
       11. A method comprising:
 providing a first source region and a first drain region forming a first L-shaped layout, the first source and drain regions being formed on a bottom gate spacer material; and 
 providing a second source region and a second drain region forming a second L-shaped layout, the first L-shaped layout and the second L-shaped layout being interrupted by a gate, wherein one of the first source and drain regions extends in a direction beyond the bottom gate spacer material to form the first L-shaped layout, wherein the direction is parallel to a lengthwise direction of the gate. 
 
     
     
       12. The method of  claim 11 , wherein:
 the first source region and the first drain region comprise epitaxial material; and 
 the second source region and the second drain region comprise epitaxial material. 
 
     
     
       13. The method of  claim 11 , wherein a stacked field-effect transistor comprises the first source region, the first drain region, the second source region, the second drain region, and the gate. 
     
     
       14. The method of  claim 11 , wherein a first portion of the first L-shaped layout overlaps a second portion of the second L-shaped layout. 
     
     
       15. The method of  claim 11 , wherein the first L-shaped layout and the second L-shaped layout have different orientations such that the first and second L-shaped layouts avoid a complete overlap. 
     
     
       16. The method of  claim 11 , wherein a first channel region associated with the first source region and the first drain region overlaps a second channel region associated with the second source region and the second drain region. 
     
     
       17. The method of  claim 11 , wherein the first source region and the first drain region are doped to be complementary to the second source region and the second drain region. 
     
     
       18. The method of  claim 11 , wherein a first end of the first L-shaped layout is configured to operatively couple to a first power source and a second end of the second L-shaped layout is configured to operatively couple to a second power source, the first end and the second end being non-overlapping. 
     
     
       19. The method of  claim 11 , wherein an overlapped end of the first L-shaped layout and the second L-shaped layout is configured to operatively couple to an output connection. 
     
     
       20. The method of  claim 11 , wherein the gate is configured to operatively coupled to an input connection in proximity to the first source and drain regions and the second source and drain regions.