Inventor
CHIANG MU-CHI
TW27 patents
⚠️ This page may combine multiple inventors who share the name “CHIANG MU-CHI”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
TAIWAN SEMICONDUCTOR MFG CO LTD
11 patentsUS9460970B2Oct 4, 2016
Control fin heights in FinFET structures
TAIWAN SEMICONDUCTOR MFG CO LTD5 citations83
US10297669B2May 21, 2019
Substrate resistor and method of making same
TAIWAN SEMICONDUCTOR MFG CO LTD2 citations73
US12520520B2Jan 6, 2026
Isolation structure for isolating source/drain region structure from adjacent source/drain structure
TAIWAN SEMICONDUCTOR MFG CO LTD0 citations62
US12300698B2May 13, 2025
Isolation structure for preventing unintentional merging of epitaxially grown source/drain
TAIWAN SEMICONDUCTOR MFG CO LTD0 citations62
US11990525B2May 21, 2024
Isolation structure for isolating epitaxially grown source/drain regions and method of fabrication thereof
TAIWAN SEMICONDUCTOR MFG CO LTD0 citations62
US11749683B2Sep 5, 2023
Isolation structure for preventing unintentional merging of epitaxially grown source/drain
TAIWAN SEMICONDUCTOR MFG CO LTD0 citations62
US11349002B2May 31, 2022
Isolation structure for for isolating epitaxially grown source/drain regions and method of fabrication thereof
TAIWAN SEMICONDUCTOR MFG CO LTD0 citations62
US11315924B2Apr 26, 2022
Isolation structure for preventing unintentional merging of epitaxially grown source/drain
TAIWAN SEMICONDUCTOR MFG CO LTD0 citations62
US12471352B2Nov 11, 2025
Semiconductor device and method of fabricating the same
TAIWAN SEMICONDUCTOR MFG CO LTD0 citations57
US10872963B2Dec 22, 2020
Substrate resistor and method of making same
TAIWAN SEMICONDUCTOR MFG CO LTD0 citations52
US9607835B2Mar 28, 2017
Semiconductor device with biased feature
TAIWAN SEMICONDUCTOR MFG CO LTD0 citations52
TAIWAN SEMICONDUCTOR MFG
9 patentsUS7564105B2Jul 21, 2009
Quasi-plannar and FinFET-like transistors on bulk silicon
TAIWAN SEMICONDUCTOR MFG138 citations98
US6500739B1Dec 31, 2002
Formation of an indium retrograde profile via antimony ion implantation to improve NMOS short channel effect
TAIWAN SEMICONDUCTOR MFG137 citations95
US6235600B1May 22, 2001
Method for improving hot carrier lifetime via a nitrogen implantation procedure performed before or after a teos liner deposition
TAIWAN SEMICONDUCTOR MFG29 citations92
US6368928B1Apr 9, 2002
Method of forming an indium retrograde profile via use of a low temperature anneal procedure to reduce NMOS short channel effects
TAIWAN SEMICONDUCTOR MFG33 citations89
US7994040B2Aug 9, 2011
Semiconductor device and fabrication thereof
TAIWAN SEMICONDUCTOR MFG11 citations80
US8975698B2Mar 10, 2015
Control fin heights in FinFET structures
TAIWAN SEMICONDUCTOR MFG4 citations72
US7371634B2May 13, 2008
Amorphous carbon contact film for contact hole etch process
TAIWAN SEMICONDUCTOR MFG5 citations62
US7649226B2Jan 19, 2010
Source and drain structures and manufacturing methods
TAIWAN SEMICONDUCTOR MFG0 citations52
USRE40138EMar 4, 2008
Method for improving hot carrier lifetime via a nitrogen implantation procedure performed before or after a Teos liner deposition
TAIWAN SEMICONDUCTOR MFG1 citations52