Inventor
KELKAR NIKHIL VISHWANATH
US28 patents
⚠️ This page may combine multiple inventors who share the name “KELKAR NIKHIL VISHWANATH”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
NAT SEMICONDUCTOR CORP
19 patentsUS6521970B1Feb 18, 2003
Chip scale package with compliant leads
NAT SEMICONDUCTOR CORP97 citations98
US6075290AJun 13, 2000
Surface mount die: wafer level chip-scale package and process for making the same
NAT SEMICONDUCTOR CORP250 citations97
US6023094AFeb 8, 2000
Semiconductor wafer having a bottom surface protective coating
NAT SEMICONDUCTOR CORP116 citations97
US6175162B1Jan 16, 2001
Semiconductor wafer having a bottom surface protective coating
NAT SEMICONDUCTOR CORP92 citations96
US6462426B1Oct 8, 2002
Barrier pad for wafer level chip scale packages
NAT SEMICONDUCTOR CORP104 citations95
US6900532B1May 31, 2005
Wafer level chip scale package
NAT SEMICONDUCTOR CORP31 citations92
US6448632B1Sep 10, 2002
Metal coated markings on integrated circuit devices
NAT SEMICONDUCTOR CORP49 citations92
US6327158B1Dec 4, 2001
Metal pads for electrical probe testing on wafer with bump interconnects
NAT SEMICONDUCTOR CORP46 citations92
US6249044B1Jun 19, 2001
Opaque metallization to cover flip chip die surface for light sensitive semiconductor devices
NAT SEMICONDUCTOR CORP38 citations92
USRE38789ESep 6, 2005
Semiconductor wafer having a bottom surface protective coating
NAT SEMICONDUCTOR CORP19 citations91
US7135385B1Nov 14, 2006
Semiconductor devices having a back surface protective coating
NAT SEMICONDUCTOR CORP43 citations90
US7015064B1Mar 21, 2006
Marking wafers using pigmentation in a mounting tape
NAT SEMICONDUCTOR CORP17 citations83
US7642175B1Jan 5, 2010
Semiconductor devices having a back surface protective coating
NAT SEMICONDUCTOR CORP9 citations81
US6972244B1Dec 6, 2005
Marking semiconductor devices through a mount tape
NAT SEMICONDUCTOR CORP12 citations79
US7241643B1Jul 10, 2007
Wafer level chip scale package
NAT SEMICONDUCTOR CORP8 citations74
US6900110B1May 31, 2005
Chip scale package with compliant leads
NAT SEMICONDUCTOR CORP8 citations74
US6398034B1Jun 4, 2002
Universal tape for integrated circuits
NAT SEMICONDUCTOR CORP7 citations74
US7282375B1Oct 16, 2007
Wafer level package design that facilitates trimming and testing
NAT SEMICONDUCTOR CORP5 citations63
US6730170B1May 4, 2004
Encapsulant material applicator for semiconductor wafers and method of use thereof
NAT SEMICONDUCTOR CORP0 citations41
Intersil Americas LLC
3 patentsUS9012267B2Apr 21, 2015
Method of manufacturing a packaged circuit including a lead frame and a laminate substrate
Intersil Americas LLC3 citations61
US8946875B2Feb 3, 2015
Packaged semiconductor devices including pre-molded lead-frame structures, and related methods and systems
Intersil Americas LLC2 citations56
US9613889B2Apr 4, 2017
Packaged circuit with a lead frame and laminate substrate
Intersil Americas LLC0 citations50