Inventor
LEVY MAX G
US35 patents
⚠️ This page may combine multiple inventors who share the name “LEVY MAX G”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
IBM
24 patentsUS6633055B2Oct 14, 2003
Electronic fuse structure and method of manufacturing
IBM69 citations96
US6388305B1May 14, 2002
Electrically programmable antifuses and methods for forming the same
IBM78 citations95
US5824580AOct 20, 1998
Method of manufacturing an insulated gate field effect transistor
IBM56 citations94
US5804490ASep 8, 1998
Method of filling shallow trenches
IBM27 citations91
US5721448AFeb 24, 1998
Integrated circuit chip having isolation trenches composed of a dielectric layer with oxidation catalyst material
IBM45 citations90
US6361402B1Mar 26, 2002
Method for planarizing photoresist
IBM26 citations89
US10050115B2Aug 14, 2018
Tapered gate oxide in LDMOS devices
IBM11 citations84
US7485965B2Feb 3, 2009
Through via in ultra high resistivity wafer and related methods
IBM10 citations84
US6812122B2Nov 2, 2004
Method for forming a voltage programming element
IBM16 citations83
US7239376B2Jul 3, 2007
Method and apparatus for correcting gravitational sag in photomasks used in the production of electronic devices
IBM10 citations82
US6121106ASep 19, 2000
Method for forming an integrated trench capacitor
IBM10 citations74
US9337310B2May 10, 2016
Low leakage, high frequency devices
IBM5 citations73
US6518145B1Feb 11, 2003
Methods to control the threshold voltage of a deep trench corner device
IBM10 citations73
US10224225B2Mar 5, 2019
Centering substrates on a chuck
IBM2 citations72
US9997385B2Jun 12, 2018
Centering substrates on a chuck
IBM2 citations72
US9685362B2Jun 20, 2017
Apparatus and method for centering substrates on a chuck
IBM3 citations72
US9548349B2Jan 17, 2017
Semiconductor device with metal extrusion formation
IBM2 citations72
US5757059AMay 26, 1998
Insulated gate field effect transistor
IBM9 citations71
US8709903B2Apr 29, 2014
Silicon-on-insulator (SOI) structure configured for reduced harmonics and method of forming the structure
IBM1 citations63
US8564067B2Oct 22, 2013
Silicon-on-insulator (SOI) structure configured for reduced harmonics and method of forming the structure
IBM0 citations52
US7842580B2Nov 30, 2010
Structure and method for buried inductors for ultra-high resistivity wafers for SOI/RF SiGe applications
IBM0 citations52
US9825119B2Nov 21, 2017
Semiconductor device with metal extrusion formation
IBM0 citations51
US9825120B2Nov 21, 2017
Semiconductor device with metal extrusion formation
IBM0 citations51
US9059258B2Jun 16, 2015
Controlled metal extrusion opening in semiconductor structure and method of forming
IBM0 citations51
GLOBALFOUNDRIES INC
4 patentsUS9508578B2Nov 29, 2016
Method and apparatus for detecting foreign material on a chuck
GLOBALFOUNDRIES INC3 citations72
US9893157B1Feb 13, 2018
Structures with contact trenches and isolation trenches
GLOBALFOUNDRIES INC4 citations71
US9595579B2Mar 14, 2017
Dual shallow trench isolation (STI) structure for field effect transistor (FET)
GLOBALFOUNDRIES INC0 citations52
US9484301B2Nov 1, 2016
Controlled metal extrusion opening in semiconductor structure and method of forming
GLOBALFOUNDRIES INC0 citations51
SIEMENS AG
2 patentsBOTULA ALAN B
2 patentsUS8698244B2Apr 15, 2014
Silicon-on-insulator (SOI) structure configured for reduced harmonics, design structure and method
BOTULA ALAN B4 citations73
US8471340B2Jun 25, 2013
Silicon-on-insulator (SOI) structure configured for reduced harmonics and method of forming the structure
BOTULA ALAN B4 citations63
LEVY MAX G
2 patentsUS8487379B2Jul 16, 2013
Structure and method for buried inductors for ultra-high resistivity wafers for SOI/RF SiGe applications
LEVY MAX G3 citations60
US8188570B2May 29, 2012
Structure and method for buried inductors for ultra-high resistivity wafers for SOI/RF SiGe applications
LEVY MAX G1 citations60