Inventor

PICKETT JAMES K

US51 patents

⚠️ This page may combine multiple inventors who share the name “PICKETT JAMES K”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

PICKETT JAMES K

ADVANCED MICRO DEVICES INC

Microcode patch device and method for patching microcode using match registers and patch routines

Superscalar microprocessor employing a way prediction unit to predict the way of an instruction fetch address and to concurrently provide a branch prediction address corresponding to the fetch address

Data transaction typing for improved caching and prefetching characteristics

Instruction fetch unit configured to provide sequential way prediction for sequential instruction fetches

Superscalar microprocessor stack structure for judging validity of predicted subroutine return addresses

Way prediction unit and a method for operating the same

Apparatus and method for independently schedulable functional units with issue lock mechanism in a processor

Superscalar microprocessor load/store unit employing a unified buffer and separate pointers for load and store operations

Superscalar microprocessor employing away prediction structure

Microprocessor employing a performance throttling mechanism for power management

Apparatus and method for tracing microprocessor instructions

Fetching instructions from an instruction cache using sequential way prediction

Stride-based data address prediction structure

Instruction redefinition using model specific registers

Computer system including priorities for memory operations and allowing a higher priority memory operation to interrupt a lower priority memory operation

Stride instruction for fetching data separated by a stride amount

Apparatus and method for tracing microprocessor instructions

Context-dependent memory-mapped registers for transparent expansion of a register file

Speculative register file for storing speculative register states and removing dependencies between instructions utilizing the register

Data memory unit and method for storing data into a lockable cache in one clock cycle by previewing the tag array

Data speculation based on stack-relative addressing patterns

System and method for linking speculative results of load operations to register values

Pipelined data cache with multiple ports and processor with load/store unit selecting only load or store operations for concurrent processing

Start of access instruction configured to indicate an access mode for fetching memory operands in a microprocessor

Speculative register storage for storing speculative results corresponding to register updated by a plurality of concurrently recorded instruction

Cache structure having a reduced tag comparison to enable data transfer from said cache

Stride-based data address prediction structure

Prefetch unit for use with a cache memory subsystem of a cache memory hierarchy

Processor with dependence mechanism to predict whether a load is dependent on older store

System and method for handling exceptional instructions in a trace cache based processor

Data speculation based on addressing patterns identifying dual-purpose register

System and method of using speculative operand sources in order to speculatively bypass load-store operations

Computer system including priorities for memory operations and allowing a higher priority memory operation to interrupt a lower priority memory operation

Way prediction structure for predicting the way of a cache in which an access hits, thereby speeding cache access time

Retaining flag value associated with dead result data in freed rename physical register with an indicator to select set-aside register instead for renaming

Variable byte-length instructions using state of function bit of second byte of plurality of instructions bytes as indicative of whether first byte is a prefix byte

Apparatus for aligning instructions using predecoded shift amounts

Cache memory subsystem including a fixed latency R/W pipeline

System and method for modifying a load operation to include a register-to-register move operation in order to forward speculative load results to a dependent operation

Integrated circuit with multiple microcode ROMs

Efficient microcode entry access from sequentially addressed portion via non-sequentially addressed portion

Functional bit identifying a prefix byte via a particular state regardless of type of instruction

Store-to-load forwarding buffer using indexed lookup

System and method to prevent in-flight instances of operations from disrupting operation replay within a data-speculative microprocessor

Speculation pointers to identify data-speculative operations in microprocessor

Load store unit with replay mechanism

DELCO ELECTRONICS CORP

Interface circuit for interfacing a peripheral device with a microprocessor operating in either a synchronous or an asynchronous mode

CMOS binary threshold comparator

CMOS binary equals comparator with carry in and out

INTEL CORP

Supporting multiple memory types in a memory slot