Microprocessor employing a performance throttling mechanism for power management

Abstract

A microprocessor includes a plurality of execution units each configured to execute instructions and an instruction dispatch circuit configured to dispatch instructions for execution by the plurality of execution units. A power management control unit includes a programmable unit for storing information specifying one or more reduced power modes. In the implementation of a first performance throttling technique, the power management control unit may be configured to cause the instruction dispatcher to limit the dispatch of instructions to a limited number of execution units. In the implementation of a second performance throttling technique, the power management control unit may be configured to limit the dispatch of instructions from the instruction dispatcher on every cycle, upon every other cycle, upon every third cycle, upon every fourth cycle, and so on. In the implementation of a third performance throttling technique, the power management control unit may be configured to control the dispatch of instructions from a floating-point scheduler to one or more floating-point execution pipelines.

What is claimed is:  
     
       1. A microprocessor comprising: 
       a plurality of execution units each configured to execute instructions;  
       an instruction dispatch circuit configured to dispatch said instructions for execution by said plurality of execution units;  
       a power management control unit coupled to said instruction dispatch circuit, wherein said power management unit includes a programmable unit for storing a particular value specifying a reduced power mode;  
       wherein said instruction dispatch circuit is configured to convey instructions to a restricted number of said plurality of execution units in response to said particular value being stored in said programmable unit;  
       a floating-point scheduler coupled to receive floating-point instructions dispatched from said instruction dispatcher;  
       at least one floating-point execution pipeline coupled to receive said floating-point instructions from said floating-point scheduler;  
       wherein said power management control unit is further configured to be programmed in a floating-point power reduced mode, wherein said floating-point scheduler is configured to stall dispatch of selected floating-point instructions to said at least one floating-point execution pipeline in response to said reduced floating-point power mode.  
     
     
       2. A microprocessor as recited in  claim 1  wherein said instruction dispatch circuit comprises an instruction alignment unit. 
     
     
       3. The microprocessor as recited in  claim 1  wherein each of said plurality of execution units is configured to execute integer instructions. 
     
     
       4. The microprocessor as recited in  claim 1  wherein each of said plurality of execution units is included within a corresponding execution pipeline. 
     
     
       5. The microprocessor as recited in  claim 4  wherein each corresponding execution pipeline includes a decode unit coupled to receive instructions from said instruction dispatch circuit and a reservation station coupled to receive a decoded instruction from said decoder. 
     
     
       6. The microprocessor as recited in  claim 1  wherein said power management control unit is configured to cause said floating-point scheduler to stall dispatch of selected floating-point instructions to said at least one floating-point execution pipeline during selected cycles. 
     
     
       7. A microprocessor comprising: 
       at least one execution unit configured to execute instructions;  
       an instruction dispatch circuit configured to dispatch said instructions for execution by said at least one execution unit;  
       a power management control unit coupled to said instruction dispatch circuit, wherein said power management unit includes a programmable unit for storing information corresponding to a reduced power mode;  
       wherein said instruction dispatch circuit is configured to stall dispatch of selected instructions to said at least one execution unit upon certain dispatch cycles in response to said information being stored in said programmable unit;  
       a floating-point scheduler coupled to receive floating-point instructions dispatched from said instruction dispatcher;  
       at least one floating-point execution pipeline coupled to receive said floating-point instructions from said floating-point scheduler;  
       wherein said power management control unit is further configured to be programmed in a floating-point power reduced mode, wherein said floating-point scheduler is configured to stall dispatch of selected floating-point instructions to said at least one floating-point execution pipeline in response to said reduced floating-point power mode.  
     
     
       8. The microprocessor as recited in  claim 7  wherein said at least one execution unit includes at least two execution units coupled in a parallel, superscalar configuration. 
     
     
       9. The microprocessor as recited in  claim 7  wherein said programmable unit includes a counter containing a value that is modified upon each dispatch cycle, wherein a particular value of said counter controls the stall of said selected instructions. 
     
     
       10. A microprocessor as recited in  claim 7  wherein said instruction dispatch circuit comprises an instruction alignment unit. 
     
     
       11. The microprocessor as recited in  claim 7  wherein each of said plurality of execution units is configured to execute integer instructions. 
     
     
       12. The microprocessor as recited in  claim 7  wherein each of said plurality of execution units is included within a corresponding execution pipeline. 
     
     
       13. The microprocessor as recited in  claim 12  wherein each corresponding execution pipeline includes a decode unit coupled to receive instructions from said instruction dispatch circuit and a reservation station coupled to receive a decoded instruction from said decoder. 
     
     
       14. The microprocessor as recited in  claim 7  wherein said power management control unit is configured to cause said floating-point scheduler to stall dispatch of said selected floating-point instructions to said at least one floating-point execution pipeline during selected cycles.