Inventor

ARONOWITZ SHELDON

US77 patents

⚠️ This page may combine multiple inventors who share the name “ARONOWITZ SHELDON”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

ARONOWITZ SHELDON

LSI LOGIC CORP

Composite semiconductor gate dielectrics

Method of forming variable thickness gate dielectrics

Method for creating self-aligned alloy capping layers for copper interconnect structures

Memory device having an electron trapping layer in a high-K dielectric gate stack

Formation of integrated circuit structure using one or more silicon layers for implantation and out-diffusion in formation of defect-free source/drain regions and also for subsequent formation of silicon nitride spacers

Low dielectric constant multiple carbon-containing silicon oxide dielectric material for use in integrated circuit structures, and method of making same

Isolation trench in semiconductor substrate with nitrogen-containing barrier region, and process for forming same

Integrated circuit structure with vertical isolation from single crystal substrate comprising isolation layer formed by implantation and annealing of noble gas atoms in substrate

Apparatus for rapid thermal processing of a wafer

Process for forming thin gate oxide with enhanced reliability by nitridation of upper surface of gate of oxide to form barrier of nitrogen atoms in upper surface region of gate oxide, and resulting product

Method of forming retrograde well structures and punch-through barriers using low energy implants

Diffusion barrier for polysilicon gate electrode of MOS device in integrated circuit structure, and method of making same

Process for forming a low dielectric constant fluorine and carbon-containing silicon oxide dielectric material

Process for forming a low dielectric constant fluorine and carbon containing silicon oxide dielectric material

Process for forming high dielectric constant gate dielectric for integrated circuit structure

Process for low energy implantation of semiconductor substrate using channeling to form retrograde wells

Method of forming a layer and semiconductor substrate

Oxide formed in semiconductor substrate by implantation of substrate with a noble gas prior to oxidation

Oxide formed in semiconductor substrate by implantation of substrate with a noble gas prior to oxidation

Process for making group IV semiconductor substrate treated with one or more group IV elements to form one or more barrier regions capable of inhibiting migration of dopant materials in substrate

Method of making integrated circuit structure with vertical isolation from single crystal substrate comprising isolation layer formed by implantation and annealing of noble gas atoms in substrate

Formation of gradient doped profile region between channel region and heavily doped source/drain contact region of MOS device in integrated circuit structure using a re-entrant gate electrode and a higher dose drain implantation

Implantation of a semiconductor substrate with controlled amount of noble gas ions to reduce channeling and/or diffusion of a boron dopant subsequently implanted into the substrate to form P- LDD region of a PMOS device

Process for forming re-entrant geometry for gate electrode of integrated circuit structure

Control and modification of dopant distribution and activation in polysilicon

Gate array layout to accommodate multi angle ion implantation

FETs having lightly doped drain regions that are shaped with counter and noncounter dorant elements

Rapid thermal processing using a narrowband infrared source and feedback

Method for reticle formation utilizing metal vaporization

Method of chemically altering a silicon surface and associated electrical devices

Depletion free polysilicon gate electrodes

Process for making group IV semiconductor substrate treated with one or more group IV elements to form barrier region capable of inhibiting migration of dopant materials in substrate

Method for forming a CMOS integrated circuit with electrostatic discharge protection

Method and apparatus for forming a memory structure having an electron affinity region

NAT SEMICONDUCTOR CORP

Method for forming isolated semiconductor structures

CMOS latchup suppression by localized minority carrier lifetime reduction

Method of providing lower contact resistance in MOS transistors

Method for forming isolated semiconductor structures

Method of providing lower contact resistance in MOS transistor structures

CMOS latchup suppression by localized minority carrier lifetime reduction

Application of electronic properties of germanium to inhibit n-type or p-type diffusion in silicon

Method of providing lower contact resistance in MOS transistor structures

Method of fabricating P-buried layers for PNP devices

Defect free CMOS process

Application of electronic properties of germanium to inhibit n-type or p-type diffusion in silicon

Method of manufacturing semiconductor device structures utilizing predictive dopant-dopant interactions

Self-aligned masking for ultra-high energy implants with application to localized buried implants and insolation structures

FAIRCHILD SEMICONDUCTOR

Modification of properties of p-type dopants with other p-type dopants

Method of controlling dopant diffusion and dopant electrical activation by implanted inert gas atoms

NAT SEMICONDUCTOR INC

Defect-free bipolar process