Inventor

NARASIMHA SHREESH

US115 patents

⚠️ This page may combine multiple inventors who share the name “NARASIMHA SHREESH”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

NARASIMHA SHREESH

IBM

High-performance CMOS devices on hybrid crystal oriented substrates

Material for contact etch layer to enhance device performance

Asymmetric high-k dielectric for reducing gate induced drain leakage

Method for avoiding oxide undercut during pre-silicide clean for thin spacer FETs

Curved FINFETs

Hybrid bulk-SOI 6T-SRAM cell for improved cell stability and performance

Method of improving the quality of defective semiconductor material

Asymmetric high-k dielectric for reducing gate induced drain leakage

Asymmetric high-K dielectric for reducing gate induced drain leakage

Asymmetric high-k dielectric for reducing gate induced drain leakage

Asymmetric high-k dielectric for reducing gate induced drain leakage

Asymmetric high-K dielectric for reducing gate induced drain leakage

Asymmetric high-K dielectric for reducing gate induced drain leakage

Asymmetric high-k dielectric for reducing gate induced drain leakage

Asymmetric high-k dielectric for reducing gate induced drain leakage

Asymmetric high-k dielectric for reducing gate induced drain leakage

Asymmetric high-k dielectric for reducing gate induced drain leakage

Asymmetric high-K dielectric for reducing gate induced drain leakage

Semiconductor structure with integrated passive structures

Germanium oxide free atomic layer deposition of silicon oxide and high-k gate dielectric on germanium containing channel for CMOS devices

Faceted intrinsic epitaxial buffer layer for reducing short channel effects while maximizing channel stress levels

Reducing dislocation formation in semiconductor devices through targeted carbon implantation

Method and structure for SOI body contact FET with reduced parasitic capacitance

Semiconductor structure and method of forming the structure

OPC trimming for performance

Halo-first ultra-thin SOI FET for superior short channel control

Dual gate dielectric SRAM

Semiconductor devices having torsional stresses

Body contact structures and methods of manufacturing the same

Semiconductor structure for low parasitic gate capacitance

Device having dual etch stop liner and reformed silicide layer and related methods

Method for forming dual etch stop liner and protective layer in a semiconductor device

Asymmetric high-k dielectric for reducing gate induced drain leakage

Low energy ion implantation of a junction butting region

Gate-all around semiconductor nanowire FETs on bulk semiconductor wafers

GLOBALFOUNDRIES INC

Merged source drain epitaxy

Device with decreased pitch contact to active regions

Fin fabrication process with dual shallow trench isolation and tunable inner and outer fin profile

Silicon nitride layer deposited at low temperature to prevent gate dielectric regrowth high-K metal gate field effect transistors

Method of forming ANA regions in an integrated circuit

Methods to control fin tip placement

BANGSARUNTIP SARUNYA

Contacts for nanowire field effect transistors

Planar and nanowire field effect transistors

Self-aligned contacts for nanowire field effect transistors

Nanowire field effect transistors

KIM BYEONG Y

Shallow trench isolation structure having a nitride plug

JOHNSON JEFFREY B

Butted SOI junction isolation structures and devices and method of fabrication

DOMENICUCCI ANTHONY G

Method of fabricating a device using low temperature anneal processes, a device and design structure

TESSERA INC

Asymmetric high-k dielectric for reducing gate induced drain leakage

SLEIGHT JEFFREY W

Gate-all around semiconductor nanowire FET&#39;s on bulk semicoductor wafers

Gate-all around semiconductor nanowire FET's on bulk semicoductor wafers