Inventor

PETTI CHRISTOPHER J

US120 patents

⚠️ This page may combine multiple inventors who share the name “PETTI CHRISTOPHER J”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

PETTI CHRISTOPHER J

SANDISK 3D LLC

Nonvolatile memory cell comprising a diode and a resistance-switching material

Selective germanium deposition for pillar devices

High bandwidth one time field-programmable memory

High density contact to relaxed geometry layers

Method for using a passive element memory array incorporating reversible polarity word line and bit line decoders

Method of programming cross-point diode memory array

Three dimensional hexagonal matrix memory array

Silicided bit line for reversible-resistivity memory

Three dimensional hexagonal matrix memory array

Passive element memory array incorporating reversible polarity word line and bit line decoders

Masking of repeated overlay and alignment marks to allow reuse of photomasks in a vertical structure

Method for reducing dielectric overetch when making contact to conductive features

Method for using a mixed-use memory array with different data states

Decoding circuit for non-binary groups of memory line drivers

High-voltage transistor and fabrication process

Method for fabricating self-aligned complementary pillar structures and wiring

Method for reducing dielectric overetch using a dielectric etch stop at a planar surface

Interleaved grouped word lines for three dimensional non-volatile storage

Vertical 1T-1R memory cells, memory arrays and methods of forming the same

Method for reducing dielectric overetch using a dielectric etch stop at a planar surface

Method for reducing dielectric overetch when making contact to conductive features

Method for forming polycrystalline thin film bipolar transistors

Method for using a memory cell comprising switchable semiconductor memory element with trimmable resistance

Programming methods to increase window for reverse write 3D cell

Method for fabricating pitch-doubling pillar structures

Method for using two data busses for memory array block selection

SANDISK TECHNOLOGIES LLC

Three-dimensional phase change memory array including discrete middle electrodes and methods of making the same

Three-dimensional phase change memory array including discrete middle electrodes and methods of making the same

Multi-state and confined phase change memory with vertical cross-point structure

Three-level ferroelectric memory cell using band alignment engineering

Three-dimensional memory device with vertical semiconductor bit lines located in recesses and method of making thereof

Resistive three-dimensional memory device with heterostructure semiconductor local bit line and method of making thereof

Content addressable memory using threshold-adjustable vertical transistors and methods of forming the same

Semiconductor die stacking using vertical interconnection by through-dielectric via structures and methods for making the same

Multi-state phase change memory device with vertical cross-point structure

Vacancy-modulated conductive oxide resistive RAM device including an interfacial oxygen source layer

MATRIX SEMICONDUCTOR INC

Semiconductor device including junction diode contacting contact-antifuse unit comprising silicide

Nonvolatile memory on SOI and compound semiconductor substrates and method of fabrication

Monolithic three dimensional array of charge storage devices containing a planarized surface

Inverted staggered thin film transistor with salicided source/drain structures and method of making same

Transistor layout configuration for tight-pitched memory array lines

Rail stack array of charge storage devices and method of making same

High-voltage transistor and fabrication process

CYPRESS SEMICONDUCTOR CORP

Method for eliminating lateral spacer erosion on enclosed contact topographies during RF sputter cleaning

Method for avoiding lithographic rounding effects for semiconductor fabrication

GTAT CORP

Mobile electronic device comprising an ultrathin sapphire cover plate

Asymmetric surface texturing for use in a photovoltaic cell and method of making

SCHEUERLEIN ROY E

Three dimensional hexagonal matrix memory array

SIVARAM SRINIVASAN

Method to form a photovoltaic cell comprising a thin lamina

HSIA KANG-JAY

Non-volatile memory arrays comprising rail stacks with a shared diode component portion for diodes of electrically isolated pillars