Inventor
WILLIAMS MICHAEL W
US48 patents
⚠️ This page may combine multiple inventors who share the name “WILLIAMS MICHAEL W”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
INTEL CORP
40 patentsUS6618791B1Sep 9, 2003
System and method for controlling power states of a memory device via detection of a chip select signal
INTEL CORP198 citations99
US6553450B1Apr 22, 2003
Buffer to multiply memory interface
INTEL CORP310 citations99
US6862653B1Mar 1, 2005
System and method for controlling data flow direction in a memory system
INTEL CORP94 citations98
US6530006B1Mar 4, 2003
System and method for providing reliable transmission in a buffered memory system
INTEL CORP112 citations98
US6463001B1Oct 8, 2002
Circuit and method for merging refresh and access operations for a memory device
INTEL CORP84 citations98
US6449213B1Sep 10, 2002
Memory interface having source-synchronous command/address signaling
INTEL CORP115 citations98
US6212611B1Apr 3, 2001
Method and apparatus for providing a pipelined memory controller
INTEL CORP134 citations98
US6507530B1Jan 14, 2003
Weighted throttling mechanism with rank based throttling for a memory system
INTEL CORP77 citations97
US6199151B1Mar 6, 2001
Apparatus and method for storing a device row indicator for use in a subsequent page-miss memory cycle
INTEL CORP86 citations97
US6604179B2Aug 5, 2003
Reading a FIFO in dual clock domains
INTEL CORP72 citations96
US6553449B1Apr 22, 2003
System and method for providing concurrent row and column commands
INTEL CORP57 citations96
US6226730B1May 1, 2001
Achieving page hit memory cycles on a virtual address reference
INTEL CORP64 citations96
US6128749AOct 3, 2000
Cross-clock domain data transfer method and apparatus
INTEL CORP46 citations95
US6772352B1Aug 3, 2004
Method and apparatus for reducing the rate of commands being issued if the rate exceeds a threshold which is based upon a temperature curve
INTEL CORP52 citations93
US6038673AMar 14, 2000
Computer system with power management scheme for DRAM devices
INTEL CORP133 citations93
US7353329B2Apr 1, 2008
Memory buffer device integrating refresh logic
INTEL CORP21 citations92
US6941484B2Sep 6, 2005
Synthesis of a synchronization clock
INTEL CORP29 citations92
US6801459B2Oct 5, 2004
Obtaining data mask mapping information
INTEL CORP17 citations92
US6400631B1Jun 4, 2002
Circuit, system and method for executing a refresh in an active memory bank
INTEL CORP28 citations92
US6370624B1Apr 9, 2002
Configurable page closing method and apparatus for multi-port host bridges
INTEL CORP22 citations92
US6252821B1Jun 26, 2001
Method and apparatus for memory address decode in memory subsystems supporting a large number of memory devices
INTEL CORP48 citations92
US6199145B1Mar 6, 2001
Configurable page closing method and apparatus for multi-port host bridges
INTEL CORP29 citations92
US7243205B2Jul 10, 2007
Buffered memory module with implicit to explicit memory command expansion
INTEL CORP11 citations84
US6957307B2Oct 18, 2005
Mapping data masks in hardware by controller programming
INTEL CORP14 citations84
US6928494B1Aug 9, 2005
Method and apparatus for timing-dependant transfers using FIFOs
INTEL CORP17 citations83
US6915399B1Jul 5, 2005
Cross-clock domain data transfer method and apparatus
INTEL CORP14 citations83
US7580465B2Aug 25, 2009
Low speed access to DRAM
INTEL CORP6 citations74
US6112306AAug 29, 2000
Self-synchronizing method and apparatus for exiting dynamic random access memory from a low power state
INTEL CORP8 citations74
US6952367B2Oct 4, 2005
Obtaining data mask mapping information
INTEL CORP6 citations73
US6154825ANov 28, 2000
Method and apparatus for addressing a memory resource comprising memory devices having multiple configurations
INTEL CORP13 citations73
US6934823B2Aug 23, 2005
Method and apparatus for handling memory read return data from different time domains
INTEL CORP4 citations63
US6385094B1May 7, 2002
Method and apparatus for achieving efficient memory subsystem write-to-read turnaround through read posting
INTEL CORP2 citations63
US6976121B2Dec 13, 2005
Apparatus and method to track command signal occurrence for DRAM data transfer
INTEL CORP5 citations62
US6829184B2Dec 7, 2004
Apparatus and method for encoding auto-precharge
INTEL CORP5 citations62
US5860128AJan 12, 1999
Method and apparatus for sampling data from a memory
INTEL CORP4 citations62
US9036718B2May 19, 2015
Low speed access to DRAM
INTEL CORP0 citations52
US6976120B2Dec 13, 2005
Apparatus and method to track flag transitions for DRAM data transfer
INTEL CORP0 citations52
US6925013B2Aug 2, 2005
Obtaining data mask mapping information
INTEL CORP0 citations52
US9910771B2Mar 6, 2018
Non-volatile memory interface
INTEL CORP0 citations51
US9535829B2Jan 3, 2017
Non-volatile memory interface
INTEL CORP1 citations51
US NAVY
5 patentsUS6701819B1Mar 9, 2004
Apparatus for launching an object in a fluid environment
US NAVY33 citations93
US6336641B1Jan 8, 2002
Break-away muzzle cap retention mechanism
US NAVY20 citations84
US6519554B1Feb 11, 2003
Computer implemented system and method for evaluating gas generator launchers
US NAVY12 citations73
US5908982AJun 1, 1999
Test apparatus for rotary drive
US NAVY13 citations70
US7445132B1Nov 4, 2008
System for determining gas cartridge actuation state
US NAVY0 citations52