Cross-clock domain data transfer method and apparatus

Abstract

An apparatus and method for transferring units of information between clock domains. A respective set of N units of information is loaded from an output circuit in a first clock domain into a storage circuit in a second clock domain during each cycle of the first clock domain. Each set of N units is selected by the output circuit to include (1) units of information that have previously loaded into the storage circuit and that will not be output from the storage output from the storage circuit prior to the storage circuit being loaded with a subsequent set of N units of information, and (2) a complement number of units of information that have not previously been loaded into the storage circuit.

1. A memory controller, comprising:
 a) a host side region to be clocked by a first clock, said host side region comprising: 
 (i) a queue to queue command packet chunks;  
 (ii) a plurality of memory command packet chunk output lanes stemming from steering circuitry, said steering circuitry to guide specific command packet chunks received from said queue to specific command packet chunk output lanes, said queue having an output for each output lane, said steering circuitry further comprising: 
 a) a first multiplexer having a first input to receive a first packet chunk from a queue output, said first multiplexer having a second input coupled to a latch circuitry output, said latch circuitry downstream from said queue output to hold a second packet chunk from said queue output;  
 b) a second multiplexer having a plurality of inputs, one of said inputs coupled to said first multiplexer's output, other inputs of said second multiplexer downstream from outputs of said queue other than said queue output; and,  
 
 
 b) a memory side region to be clocked by a second clock, said memory side region comprising:  
 inputs coupled to said memory command packet chunk output lanes.  
 
   
   
     2. The memory controller of  claim 1  further comprising shift logic on said memory side region to receive memory command packet chunks from said memory side region inputs. 
   
   
     3. The memory controller of  claim 1  wherein said steering circuitry is to guide specific row command packet chunks to said specific command packet chunk output lanes, said queue to queue row command packet chunks. 
   
   
     4. The memory controller of  claim 1  wherein said steering circuitry is to guide specific row command packet chunks to said specific command packet chunk output lanes, said queue to queue row command packet chunks. 
   
   
     5. The memory controller of  claim 1  further comprising a third multiplexer having a first input coupled to said queue output and a second input coupled to a path that propagates command packets chunks that do not enter said queue, said latch circuitry coupled to said third multiplexer's output to receive command packet chunks from said third multiplexers output. 
   
   
     6. The memory controller of  claim 5  wherein said third multiplexer further comprises a third input coupled to an output of said latch circuitry. 
   
   
     7. The memory controller of  claim 1  wherein said steering circuitry further comprises a third multiplexer having a first input coupled an output of said second multiplexer, said third multiplexer having a second input coupled to a path that propagates command packets chunks that do not enter said queue. 
   
   
     8. The memory controller of  claim 7  further comprising logic circuitry between said third multiplexer and an output lane to insert a null packet chunk onto said output lane. 
   
   
     9. An apparatus, comprising:
 a memory controller, comprising:  
 a) a host side region to be clocked by a first clock, said host side region comprising: 
 (i) a queue to queue command packet chunks;  
 (ii) a plurality of memory command packet chunk output lanes stemming from steering circuitry, said steering circuitry to guide specific command packet chunks received from said queue to specific command packet chunk output lanes, said queue having an output for each output lane, said steering circuitry further comprising: 
 a) a first multiplexer having a first input to receive a first packet chunk from a queue output, said first multiplexer having a second input coupled to a latch circuitry output, said latch circuitry downstream from said queue output to hold a second packet chunk from said queue output;  
 b) a second multiplexer having a plurality of inputs, one of said inputs coupled to said first multiplexer's output, other inputs of said second multiplexer downstream from outputs of said queue other than said queue output;  
 
 
 b) a memory side region to be clocked by a second clock, said memory side region comprising:  
 inputs coupled to said memory command packet chunk output lanes; and,  
 DRAM memory coupled to said memory side region of said memory controller.  
 
   
   
     10. The apparatus of  claim 9  further comprising shift logic on said memory side region to receive memory command packet chunks from said memory side region inputs. 
   
   
     11. The apparatus of  claim 9  wherein said steering circuitry is to guide specific row command packet chunks to said specific command packet chunk output lanes, said queue to queue row command packet chunks. 
   
   
     12. The apparatus of  claim 9  wherein said steering circuitry is to guide specific row command packet chunks to said specific command packet chunk output lanes, said queue to queue row command packet chunks. 
   
   
     13. The apparatus of  claim 9  further comprising a third multiplexer having a first input coupled to said queue output and a second input coupled to a path that propagates command packets chunks that do not enter said queue, said latch circuitry coupled to said third multiplexer's output to receive command packet chunks from said third multiplexer's output. 
   
   
     14. The apparatus of  claim 13  wherein said third multiplexer further comprises a third input coupled to an output of said latch circuitry. 
   
   
     15. The apparatus of  claim 9  wherein said steering circuitry further comprises a third multiplexer having a first input coupled an output of said second multiplexer, said third multiplexer having a second input coupled to a path that propagates command packets chunks that do not enter said queue. 
   
   
     16. The apparatus of  claim 15 , further comprising logic circuitry between said third multiplexer and an output lane to insert a null packet chunk onto said output lane.