Inventor
AMINI NADER
US23 patents
⚠️ This page may combine multiple inventors who share the name “AMINI NADER”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
IBM
22 patentsUS5542055AJul 30, 1996
System for counting the number of peripheral buses in each hierarch connected to primary bus for creating map of peripheral buses to locate peripheral devices
IBM180 citations99
US5396602AMar 7, 1995
Arbitration logic for multiple bus computer system
IBM164 citations99
US5581714ADec 3, 1996
Bus-to-bus read prefetch logic for improving information transfers in a multi-bus information handling system (bus-to-bus bridge for a multiple bus information handling system that optimizes data transfers between a system bus and a peripheral bus)
IBM135 citations98
US5450551ASep 12, 1995
System direct memory access (DMA) support logic for PCI based computer system
IBM140 citations98
US5381538AJan 10, 1995
DMA controller including a FIFO register and a residual register for data buffering and having different operating modes
IBM130 citations98
US5548786AAug 20, 1996
Dynamic bus sizing of DMA transfers
IBM128 citations96
US5499346AMar 12, 1996
Bus-to-bus bridge for a multiple bus information handling system that optimizes data transfers between a system bus and a peripheral bus
IBM84 citations96
US5544346AAug 6, 1996
System having a bus interface unit for overriding a normal arbitration scheme after a system resource device has already gained control of a bus
IBM58 citations95
US5522050AMay 28, 1996
Bus-to-bus bridge for a multiple bus information handling system that optimizes data transfers between a system bus and a peripheral bus
IBM85 citations95
US5448703ASep 5, 1995
Method and apparatus for providing back-to-back data transfers in an information handling system having a multiplexed bus
IBM74 citations95
US5313627AMay 17, 1994
Parity error detection and recovery
IBM71 citations95
US5265211ANov 23, 1993
Arbitration control logic for computer system having dual bus architecture
IBM84 citations95
US5255374AOct 19, 1993
Bus interface logic for computer system having dual bus architecture
IBM74 citations94
US5644729AJul 1, 1997
Bidirectional data buffer for a bus-to-bus interface unit in a computer system
IBM65 citations92
US5564026AOct 8, 1996
Bus-to-bus pacing logic for improving information transfers in a multi-bus information handling system
IBM35 citations92
US5333274AJul 26, 1994
Error detection and recovery in a DMA controller
IBM52 citations92
US5301282AApr 5, 1994
Controlling bus allocation using arbitration hold
IBM26 citations92
US5966728AOct 12, 1999
Computer system and method for snooping date writes to cacheable memory locations in an expansion memory device
IBM45 citations91
US5761533AJun 2, 1998
Computer system with varied data transfer speeds between system components and memory
IBM33 citations91
US5673414ASep 30, 1997
Snooping of I/O bus and invalidation of processor cache for memory data transfers between one I/O device and cacheable memory in another I/O device
IBM24 citations91
US5659696AAug 19, 1997
Method and apparatus for determining address location and taking one of two actions depending on the type of read/write data transfer required
IBM40 citations91
US5551009AAug 27, 1996
Expandable high performance FIFO design which includes memory cells having respective cell multiplexors
IBM13 citations70