Inventor

ZAHURAK JOHN K

US150 patents

⚠️ This page may combine multiple inventors who share the name “ZAHURAK JOHN K”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

ZAHURAK JOHN K

MICRON TECHNOLOGY INC

Methods of forming recessed access devices associated with semiconductor constructions

Methods of forming capacitors, DRAM arrays, and monolithic integrated circuits

Charge storage apparatus and methods

Localized biasing for silicon on insulator structures

Process for improving roughness of conductive layer

Increased interior volume for integrated memory cell

Semiconductor processing methods of forming integrated circuitry memory devices, methods of forming capacitor containers, methods of making electrical connection to circuit nodes and related integrated circuitry

Semiconductor processing methods of forming integrated circuitry memory devices, methods of forming capacitor containers, methods of making electrical connection to circuit nodes and related integrated circuitry

Capacitors and DRAM arrays

Silicon on insulator DRAM process utilizing both fully and partially depleted devices

Methods of forming capacitors DRAM arrays, and monolithic integrated circuits

Methods of forming capacitors, DRAM arrays, and monolithic integrated circuits

Methods of forming storage capacitors in integrated circuitry memory cells and integrated circuitry

Process for forming capacitor over bit line memory cell

Process for improving roughness of conductive layer

Methods of forming capacitors and DRAM arrays

Semiconductor processing method of providing a conductively doped layer of hemispherical grain polysilicon

Three dimensional memory and methods of forming the same

Three dimensional memory and methods of forming the same

Three dimensional memory and methods of forming the same

Localized biasing for silicon on insulator structures

Method of forming fully-depleted (FD) SOI MOSFET access transistor

Silicon on insulator DRAM process utilizing both fully and partially depleted devices

Method of forming a dual-gated semiconductor-on-insulator device

Capacitor structures, DRAM cell structures, and integrated circuitry, and methods of forming capacitor structures, integrated circuitry and DRAM cell structures

SOI DRAM with buried capacitor under the digit lines utilizing a self aligning penetrating storage node contact formation

Structure for improving static refresh

Methods for forming contact and container structures, and integrated circuit devices therefrom

Methods of forming a capacitor and methods of forming a monolithic integrated circuit

Capacitor over bit line memory cell and process

Semiconductor processing methods of forming integrated circuitry memory devices, methods of forming capacitor containers, methods of making electrical connection to circuit nodes and related integrated circuitry

Capacitor structures, DRAM cell structures, and integrated circuitry, and methods of forming capacitor structures, integrated circuitry and DRAM cell structures

Methods of forming capacitors structures and DRAM cells

High pressure anneals of integrated circuit structures

Increased interior volume for integrated memory cell

Semiconductor processing methods of forming a conductive projection and methods of increasing alignment tolerances

Method of fabricating a semiconductor device utilizing polysilicon grains

Methods of forming recessed access devices associated with semiconductor constructions

TANG SANH D

Methods of forming memory cells

Three dimensional memory and methods of forming the same

Semiconductor charge storage apparatus and methods

Semiconductor cells, arrays, devices and systems having a buried conductive line and methods for forming the same

Semiconductor cells, arrays, devices and systems having a buried conductive line and methods for forming the same

Methods, structures and devices for increasing memory density

SANDHU GURTEJ

Vertically-oriented semiconductor selection device providing high drive current in cross-point array memory

Vertically-oriented semiconductor selection device for cross-point array memory

PAREKH KUNAL R

Methods of forming recessed access devices associated with semiconductor constructions

Semiconductor structures

(unassigned)

Semiconductor processing method of providing a conductively doped layer of hemispherical grain polysilicon and a hemispherical grain polysilicon layer produced according to the method

RAMASWAMY D V NIRMAL

Methods of forming resistive memory elements