Inventor

JAN CHIA-HONG

US149 patents

⚠️ This page may combine multiple inventors who share the name “JAN CHIA-HONG”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

JAN CHIA-HONG

INTEL CORP

Method of fabricating a field effect transistor structure with abrupt source/drain junctions

Device having spacers for improved salicide resistance on polysilicon gates

Device having thin first spacers and partially recessed thick second spacers for improved salicide resistance on polysilicon gates

Method of recessing spacers to improved salicide resistance on polysilicon gates

Transistor with low resistance tip and method of fabrication in a CMOS process

Device structure and method for reducing silicide encroachment

Method for making a dual damascene interconnect using a multilayer hard mask

Transistor with ultra shallow tip and method of fabrication

Method of forming a transistor

Transistor with ultra shallow tip and method of fabrication

Semiconductor device having deposited silicon regions and a method of fabrication

Transistor with minimal junction capacitance and method of fabrication

Field effect transistor structure with abrupt source/drain junctions

Method of fabricating a field effect transistor structure with abrupt source/drain junctions

Method of fabricating a field effect transistor structure with abrupt source/drain junctions

Method of fabricating a MOS transistor with a raised source/drain extension

Device structure and method for reducing silicide encroachment

Device structure and method for reducing silicide encroachment

Manufacturable dielectric formed using multiple oxidation and anneal steps

Structure and manufacturing process of localized shunt to reduce electromigration failure of copper dual damascene process

Penetrating implant for forming a semiconductor device

Selective spacer formation on transistors of different classes on the same device

Device with recessed thin and thick spacers for improved salicide resistance on polysilicon gates

Method and device for improved salicide resistance on polysilicon gates

Method and device for improved salicide resistance on polysilicon gates

Polysilicon/amorphous silicon composite gate electrode

Method for forming a polysilicon/amorphous silicon composite gate electrode

Microcrystalline silicon structure and fabrication process

Process for fabricating a microcrystalline silicon structure

Non-planar I/O and logic semiconductor devices having different workfunction on common substrate

Methods of integrating multiple gate dielectric transistors on a tri-gate (finFET) process

High voltage three-dimensional devices having dielectric liners

Antifuse element using spacer breakdown

Dielectric and isolation lower fin material for fin-based electronics

Transistor architecture having extended recessed spacer and source/drain regions and method of making same

Programmable/re-programmable device in high-k metal gate MOS

Non-planar I/O and logic semiconductor devices having different workfunction on common substrate

Non-planar I/O and logic semiconductor devices having different workfunction on common substrate

Monolithic integration of high voltage transistors and low voltage non-planar transistors

Non-planar I/O and logic semiconductor devices having different workfunction on common substrate

Planar device on fin-based transistor architecture

Planar device on fin-based transistor architecture

Transistor with airgap spacer

HAFEZ WALID M

Memory cell using BTI effects in high-k metal gate MOS

Antifuse element utilizing non-planar topology

High voltage three-dimensional devices having dielectric liners

High voltage three-dimensional devices having dielectric liners

WISCONSIN ALUMNI RES FOUND

Process for preparing schottky diode contacts with predetermined barrier heights

MURTHY ANAND S

Field effect transistor structure with abrupt source/drain junctions

YEH JENG-YA D

Precision resistor for non-planar semiconductor device architecture