P

Inventor

KEATING STEVEN J

US31 patents
⚠️ This page may combine multiple inventors who share the name “KEATING STEVEN J”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

INTEL CORP

20 patents
US6521964B1Feb 18, 2003

Device having spacers for improved salicide resistance on polysilicon gates

INTEL CORP241 citations99
US6509618B2Jan 21, 2003

Device having thin first spacers and partially recessed thick second spacers for improved salicide resistance on polysilicon gates

INTEL CORP239 citations99
US6506652B2Jan 14, 2003

Method of recessing spacers to improved salicide resistance on polysilicon gates

INTEL CORP239 citations99
US6858483B2Feb 22, 2005

Integrating n-type and p-type metal gate transistors

INTEL CORP81 citations98
US7494858B2Feb 24, 2009

Transistor with improved tip profile and method of manufacture thereof

INTEL CORP104 citations97
US7316949B2Jan 8, 2008

Integrating n-type and p-type metal gate transistors

INTEL CORP50 citations96
US6972225B2Dec 6, 2005

integrating n-type and P-type metal gate transistors

INTEL CORP54 citations96
US6953719B2Oct 11, 2005

Integrating n-type and p-type metal gate transistors

INTEL CORP62 citations96
US7821044B2Oct 26, 2010

Transistor with improved tip profile and method of manufacture thereof

INTEL CORP32 citations92
US6777760B1Aug 17, 2004

Device with recessed thin and thick spacers for improved salicide resistance on polysilicon gates

INTEL CORP13 citations92
US6593633B2Jul 15, 2003

Method and device for improved salicide resistance on polysilicon gates

INTEL CORP16 citations92
US6188117B1Feb 13, 2001

Method and device for improved salicide resistance on polysilicon gates

INTEL CORP16 citations92
US6235598B1May 22, 2001

Method of using thick first spacers to improve salicide resistance on polysilicon gates

INTEL CORP8 citations82
US6797622B2Sep 28, 2004

Selective etching of polysilicon

INTEL CORP14 citations81
US6667232B2Dec 23, 2003

Thin dielectric layers and non-thermal formation thereof

INTEL CORP6 citations73
US7211872B2May 1, 2007

Device having recessed spacers for improved salicide resistance on polysilicon gates

INTEL CORP1 citations63
US6271096B1Aug 7, 2001

Method and device for improved salicide resistance on polysilicon gates

INTEL CORP2 citations63
US6268254B1Jul 31, 2001

Method and device for improved salicide resistance on polysilicon gates

INTEL CORP1 citations63
US6251762B1Jun 26, 2001

Method and device for improved salicide resistance on polysilicon gates

INTEL CORP5 citations63
US7927959B2Apr 19, 2011

Method of patterning a metal on a vertical sidewall of an excavated feature, method of forming an embedded MIM capacitor using same, and embedded memory device produced thereby

INTEL CORP3 citations61

APPLE INC

9 patents

STEIGERWALD JOSEPH M

1 patent

KEATING STEVEN J

1 patent