Inventor
MYERS ALAN
US25 patents
⚠️ This page may combine multiple inventors who share the name “MYERS ALAN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
INTEL CORP
21 patentsUS6521964B1Feb 18, 2003
Device having spacers for improved salicide resistance on polysilicon gates
INTEL CORP241 citations99
US6509618B2Jan 21, 2003
Device having thin first spacers and partially recessed thick second spacers for improved salicide resistance on polysilicon gates
INTEL CORP239 citations99
US6506652B2Jan 14, 2003
Method of recessing spacers to improved salicide resistance on polysilicon gates
INTEL CORP239 citations99
US7227257B2Jun 5, 2007
Cooling micro-channels
INTEL CORP17 citations92
US6777760B1Aug 17, 2004
Device with recessed thin and thick spacers for improved salicide resistance on polysilicon gates
INTEL CORP13 citations92
US6593633B2Jul 15, 2003
Method and device for improved salicide resistance on polysilicon gates
INTEL CORP16 citations92
US6188117B1Feb 13, 2001
Method and device for improved salicide resistance on polysilicon gates
INTEL CORP16 citations92
US6981849B2Jan 3, 2006
Electro-osmotic pumps and micro-channels
INTEL CORP20 citations91
US6649515B2Nov 18, 2003
Photoimageable material patterning techniques useful in fabricating conductive lines in circuit structures
INTEL CORP35 citations89
US9754886B2Sep 5, 2017
Semiconductor interconnect structures
INTEL CORP5 citations84
US6861274B2Mar 1, 2005
Method of making a SDI electroosmotic pump using nanoporous dielectric frit
INTEL CORP13 citations84
US7458783B1Dec 2, 2008
Method and apparatus for improved pumping medium for electro-osmotic pumps
INTEL CORP11 citations83
US9064872B2Jun 23, 2015
Semiconductor interconnect structures
INTEL CORP8 citations82
US6235598B1May 22, 2001
Method of using thick first spacers to improve salicide resistance on polysilicon gates
INTEL CORP8 citations82
US7842553B2Nov 30, 2010
Cooling micro-channels
INTEL CORP6 citations74
US9455224B2Sep 27, 2016
Semiconductor interconnect structures
INTEL CORP3 citations73
US7211872B2May 1, 2007
Device having recessed spacers for improved salicide resistance on polysilicon gates
INTEL CORP1 citations63
US6271096B1Aug 7, 2001
Method and device for improved salicide resistance on polysilicon gates
INTEL CORP2 citations63
US6268254B1Jul 31, 2001
Method and device for improved salicide resistance on polysilicon gates
INTEL CORP1 citations63
US6251762B1Jun 26, 2001
Method and device for improved salicide resistance on polysilicon gates
INTEL CORP5 citations63
US7667319B2Feb 23, 2010
Electroosmotic pump using nanoporous dielectric frit
INTEL CORP1 citations52