Inventor

RISCH LOTHAR

DE56 patents

⚠️ This page may combine multiple inventors who share the name “RISCH LOTHAR”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

RISCH LOTHAR

SIEMENS AG

Electrically programmable memory cell arrangement and method for its manufacture

Method of producing and arrangement containing self-amplifying dynamic MOS transistor memory cells

Method of producing a read-only storage cell arrangement

Read-only-memory cell arrangement using vertical MOS transistors and gate dielectrics of different thicknesses and method for its production

Method for manufacturing an integrated circuit having at least one MOS transistor

Process of making a dram cell arrangement

Photo-transistor in MOS thin-film technology and method for production and operation thereof

Process of reducing density of fast surface states in MOS devices

Read-only memory cell arrangement and method for its production

DRAM cell arrangement and method for its manufacture

Microelectronic component and process for its production

Arrangement with self-amplifying dynamic MOS transistor storage cells

Single-electron memory cell configuration

Method for production of a read-only-memory cell arrangement having vertical MOS transistors

Method for producing a DRAM cellular arrangement

Integrated circuit structure having at least one CMOS-NAND gate and method for the manufacture thereof

Circuit arrangement with at least four transistors, and method for the manufacture thereof

SRAM cell configuration and method for its fabrication

Integrated CMOS circuit configuration, and production of same

Read-only memory cell array and process for manufacturing it

Process for making a contact betwen a capacitor electrode disposed in a trench and an MOS transistor source/drain region disposed outside the trench

Voltage-stable sub-μm MOS transistor for VLSI circuits

Arrangement for contact-free measurement of electrical charge images in electro-radiographic recording methods

Method for DRAM cell arrangement and method for its production

DRAM cell arrangement and method for its production

Method for manufacturing a micro-electronic component having an electrically conductive tip of doped silicon

INFINEON TECHNOLOGIES AG

MOS transistor, method for fabricating a MOS transistor and method for fabricating two complementary MOS transistors

Memory cell configuration, method for fabricating it and methods for operating it

Memory cell configuration

DRAM cell circuit

DRAM cell configuration and method for its production

DRAM memory cell

Nonvolatile semiconductor memory cell and method for fabricating the memory cell

Memory cell configuration, magnetic ram, and associative memory

Memory cell configuration and method for its production

DRAM cell structure with tunnel barrier

Method for producing a vertical semiconductor transistor component and vertical semiconductor transistor component

Double gate MOSFET transistor and method for the production thereof

Optoelectronic microelectronic system

Method for the production of a DRAM cell configuration

Circuit configuration having single-electron components, a method for its operation and use of the method for addition of binary numbers

Memory cell configuration and fabrication method

Static random access memory (SRAM)

Circuit configuration having at least one nanoelectronic component and method for fabricating the component

Method of producing a vertical MOS transistor

Circuit configuration with single-electron components, and operating method

INFINEON TECHNOLOGIES RICHMOND

Double gated transistor

Double gated transistor

INFINEON TECHNOLOGIES CORP

Memory cell having trench capacitor and vertical, dual-gated transistor

QIMONDA AG

Integrated circuit including a gate electrode