MOS transistor, method for fabricating a MOS transistor and method for fabricating two complementary MOS transistors

Abstract

A MOS transistor and a method for fabricating the same include producing a well doped by a first conductivity type in a semiconductor substrate. An epitaxial layer having a dopant concentration of less than 10 17 cm −3 is disposed on a surface of the doped well. Source/drain regions doped by a second conductivity type, opposite to the first conductivity type, and a channel region, are disposed in the epitaxial layer, and their depth is less than or equal to the thickness of the epitaxial layer. A method for fabricating two complementary MOS transistors is also provided.

We claim:  
     
       1. A MOS transistor, comprising: 
       a semiconductor substrate;  
       a well doped by a first conductivity type in said semiconductor substrate, said doped well having a surface;  
       an epitaxial layer having a dopant concentration of less than 10 17  cm −3  and a given thickness, said epitaxial layer disposed on said surface of said doped well;  
       source/drain regions doped by a second conductivity type opposite to said first conductivity type, said source/drain regions disposed in said epitaxial layer, and said source/drain regions having a depth at most equal to said given thickness;  
       a channel region disposed in said epitaxial layer;  
       a first doped layer doped by said first conductivity type and disposed in said epitaxial layer between said source/drain regions, said first doped layer having a depth smaller than said depth of said source/drain regions and a thickness smaller than said given thickness of said epitaxial layer; and  
       a second doped layer doped by said first conductivity type and disposed underneath said first doped layer in said epitaxial layer.  
     
     
       2. The MOS transistor according to  claim 1 , wherein said given thickness of said epitaxial layer is between 100 and 200 nm. 
     
     
       3. The MOS transistor according to  claim 1 , wherein said doped layer is disposed at a depth of between 10 and 50 nm, has a thickness of between 10 and 50 nm and has a dopant concentration of between 5×10 17  and 5×10 18  cm −3 . 
     
     
       4. The MOS transistor according to  claim 1 , wherein said second doped layer is disposed at a depth of between 50 and 200 nm, has a thickness of between 10 and 50 nm and has a dopant concentration of between 10 17  and 5×10 18  cm −3 .