Inventor

PARUCHURI VAMSI K

US63 patents

⚠️ This page may combine multiple inventors who share the name “PARUCHURI VAMSI K”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

PARUCHURI VAMSI K

IBM

Selective implementation of barrier layers to achieve threshold voltage control in CMOS device fabrication with high k dielectrics

Planar and non-planar CMOS devices with multiple tuned threshold voltages

Metal gate CMOS with at least a single gate metal and dual gate dielectrics

Selective implementation of barrier layers to achieve threshold voltage control in CMOS device fabrication with high-k dielectrics

Fin cut enabling single diffusion breaks

Complementary metal oxide semiconductor replacement gate high-k metal gate devices with work function adjustments

Selective implementation of barrier layers to achieve threshold voltage control in CMOS device fabrication with high-k dielectrics

Techniques for enabling multiple Vt devices using high-K metal gate stacks

Using metal/metal nitride bilayers as gate electrodes in self-aligned aggressively scaled CMOS devices

Selective implementation of barrier layers to achieve threshold voltage control in CMOS device fabrication with high k dielectrics

Stabilization of flatband voltages and threshold voltages in hafnium oxide based silicon transistors for CMOS

Nitrogen-containing field effect transistor gate stack containing a threshold voltage control layer formed via deposition of a metal oxide

Introduction of metal impurity to change workfunction of conductive electrodes

CMOS transistors with differential oxygen content high-k dielectrics

Dual metal gate self-aligned integration

In-place bonding of microstructures

Self-forming barrier for subtractive copper

High performance CMOS circuits, and methods for fabricating same

CMOS transistors with differential oxygen content high-K dielectrics

Using metal/metal nitride bilayers as gate electrodes in self-aligned aggressively scaled CMOS devices

Dual metal gate self-aligned integration

Advanced high-k gate stack patterning and structure containing a patterned high-k gate stack

Complementary metal oxide semiconductor device with an electroplated metal replacement gate

Selective implementation of barrier layers to achieve threshold voltage control in CMOS device fabrication with high K dielectrics

Metal gate CMOS with at least a single gate metal and dual gate dielectrics

Method of fabricating a metal gate CMOS with at least a single gate metal and dual gate dielectrics

Metal gates with low charge trapping and enhanced dielectric reliability characteristics for high-k gate dielectric stacks

Introduction of metal impurity to change workfunction of conductive electrodes

Multilayer dielectric structures for semiconductor nano-devices

Multilayer dielectric structures for semiconductor nano-devices

Complementary metal oxide semiconductor replacement gate high-K metal gate devices with work function adjustments

Ultrathin multilayer metal alloy liner for nano Cu interconnects

Method of fabricating a semiconductor structure including one device region having a metal gate electrode located atop a thinned polygate electrode

Method and apparatus for flatband voltage tuning of high-k field effect transistors

Metal oxynitride as a pFET material

In-place bonding of microstructures

Metal oxynitride as a pFET material

Complementary metal oxide semiconductor replacement gate high-k metal gate devices with work function adjustments

JAGANNATHAN HEMANTH

Replacement gate electrode with multi-thickness conductive metallic nitride layers

Replacement gate electrode with multi-thickness conductive metallic nitride layers

Structure and method to obtain EOT scaled dielectric stacks

FRANK MARTIN M

Techniques for enabling multiple Vt devices using high-K metal gate stacks

Techniques for enabling multiple Vt devices using high-K metal gate stacks

GLOBALFOUNDRIES INC

Wafer bonding for 3D device packaging fabrication

Changing effective work function using ion implantation during dual work function metal gate integration

CHENG KANGGUO

Method for integrating multiple threshold voltage devices for CMOS

BOJARCZUK JR NESTOR A

Selective implementation of barrier layers to achieve threshold voltage control in CMOS device fabrication with high-k dielectrics

GUHA SUPRATIK

Method and apparatus for flatband voltage tuning of high-k field effect transistors

CHUDZIK MICHAEL P

Changing effective work function using ion implantation during dual work function metal gate integration

ANDO TAKASHI

Method and apparatus for fabricating a high-performance band-edge complementary metal-oxide-semiconductor device