Inventor

EICKEMEYER RICHARD J

US37 patents

⚠️ This page may combine multiple inventors who share the name “EICKEMEYER RICHARD J”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

EICKEMEYER RICHARD J

IBM

Improved method to prefetch load instruction data

In-memory preprocessor for compounding a sequence of instructions for parallel computer system execution

Method of indicating parallel execution compoundability of scalar instructions based on analysis of presumed instructions

Predecode instruction compounding

System for comounding instructions in a byte stream prior to fetching and identifying the instructions for execution

Memory management for scalable compound instruction set machines with in-memory compounding

Background completion of instruction and associated fetch request in a multithread processor

Address prediction to avoid address generation interlocks in computer systems

Data processing system, processor and method of data processing having improved branch target address cache

Method for resource balancing using dispatch flush in a simultaneous multithread processor

Method and apparatus for evaluating integrated circuit design performance using enhanced basic block vectors that include data dependent information

Adaptive fetch gating in multithreaded processors, fetch control and method of controlling fetches

Prefetch performance

Techniques for dynamic sequential instruction prefetching

Managing a divided load reorder queue

Predicting indirect branches using problem branch filtering and pattern cache

Dependency skipping in a load-compare-jump sequence of instructions by incorporating compare functionality into the jump instruction and auto-finishing the compare instruction

Inferring future value for speculative branch resolution in a microprocessor

Dynamic sequential instruction prefetching

Method, system, and computer program product for path-correlated indirect address predictions

Instruction prefetching in a computer processor using a prefetch prediction vector

Flushing of instructions based upon a finish ratio and/or moving a flush point in a processor

Splitting load hit store table for out-of-order processor

Prefetch performance

System for allowing only a partial value prediction field/cache size

Inferring future value for speculative branch resolution

Dependency skipping execution

Instruction prefetching in a computer processor using a prefetch prediction vector

Splitting load hit store table for out-of-order processor

Thread priorities using misprediction rate and speculative depth

Prefetch confidence and phase prediction for improving prefetch performance in bandwidth constrained scenarios

Effective address table with multiple taken branch handling for out-of-order processors

Techniques for predicting a target address of an indirect branch instruction

Accessing partial cachelines in a data cache

Tracking long GHV in high performance out-of-order superscalar processors

BELL JR ROBERT H

Scaling instruction intervals to identify collection points for representative instruction traces

DALE JASON N

Persistent prefetch data stream settings