Inventor · disambiguated record
Tetsuhiko Okada
Also filed as: OKADA TETSUHIKO
20 granted patents·3 pending applications·415 citations·filing 1989–2006
96Inventor score
Top patents by PatentIndex Score
23 records- 0185US5652858AMethod for prefetching pointer-type data structure and information processing apparatus thereforHITACHI LTD·Filed 1995·Granted Jul 29, 1997·126 cites·17 claims
- 0278US6516391B1Multiprocessor system and methods for transmitting memory access transactions for the sameHITACHI LTD·Filed 2000·Granted Feb 4, 2003·28 cites·10 claims
- 0371US6219735B1Method for controlling a bus to progress transfer cycles without inserting a cycle for acknowledgementHITACHI LTD·Filed 2000·Granted Apr 17, 2001·9 cites·6 claims
- 0469US6591325B1Method and apparatus of out-of-order transaction processing using request side queue pointer and response side queue pointerHITACHI LTD·Filed 2000·Granted Jul 8, 2003·14 cites·8 claims
- 0567US6011791AMulti-processor system and its networkHITACHI LTD·Filed 1996·Granted Jan 4, 2000·51 cites·2 claims
- 0665US5428753AMethod for controlling a bus to progress transfer cycles without inserting a cycle for acknowledgmentHITACHI LTD·Filed 1993·Granted Jun 27, 1995·24 cites·12 claims
- 0756US6728258B1Multi-processor system and its networkHITACHI LTD·Filed 1999·Granted Apr 27, 2004·31 cites·5 claims
- 0856US5873122AMemory system performing fast access to a memory location by omitting transfer of a redundant addressHITACHI LTD·Filed 1997·Granted Feb 16, 1999·22 cites·54 claims
- 0953US5408625AMicroprocessor capable of decoding two instructions in parallelHITACHI LTD·Filed 1993·Granted Apr 18, 1995·26 cites·3 claims
- 1052US6292867B1Data processing systemHITACHI LTD·Filed 2000·Granted Sep 18, 2001·2 cites·10 claims
- 1147US5678062AInput/output control method and data processorHITACHI LTD·Filed 1994·Granted Oct 14, 1997·19 cites·23 claims
- 1247US5148532APipeline processor with prefetch circuitHITACHI LTD·Filed 1990·Granted Sep 15, 1992·19 cites·10 claims
- 1346US5657458AMethod for controlling a bus to progress transfer cycles without inserting a cycle for acknowledgmentHITACHI LTD·Filed 1995·Granted Aug 12, 1997·10 cites·20 claims
- 1446US2003084218A1Method for controlling a bus to progress transfer cycles without inserting a cycle for acknowledgmentFiled 2002·Application pending·0 cites
- 1545USRE41589EMemory system performing fast access to a memory location by omitting the transfer of a redundant addressRENESAS TECH CORP·Filed 2002·Granted Aug 24, 2010·0 cites·47 claims
- 1645US2006174301A1Video clip display deviceHASHIMOTO HIDEKI·Filed 2006·Application pending·0 cites
- 1744US2001016888A1Method for controlling a bus to progress transfer cycles without inserting a cycle for acknowledgmentHITACHI LTD·Filed 2001·Application pending·0 cites
- 1843US5774679AMethod for controlling a bus to progress transfer cycles without inserting a cycle for acknowledgementHITACHI LTD·Filed 1996·Granted Jun 30, 1998·8 cites·50 claims
- 1941US5604874AMethod for controlling a bus to progress transfer cycles without inserting a cycle for acknowledgmentHITACHI LTD·Filed 1995·Granted Feb 18, 1997·7 cites·42 claims
- 2040US6047345AMethod for controlling a bus to progress transfer cycles without inserting a cycle for acknowledgmentHITACHI LTD·Filed 1998·Granted Apr 4, 2000·6 cites·2 claims
- 2140US5590290AMethod for controlling a bus to progress transfer cycles without inserting a cycle for acknowledgementHITACHI LTD·Filed 1995·Granted Dec 31, 1996·6 cites·21 claims
- 2236US5220670AMicroprocessor having ability to carry out logical operation on internal busHITACHI LTD·Filed 1989·Granted Jun 15, 1993·6 cites·8 claims
- 2329US6154807AMemory system performing fast access to a memory location by omitting the transfer of a redundant addressHITACHI LTD·Filed 1998·Granted Nov 28, 2000·1 cites·4 claims
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