Inventor
WANG TSING-CHOW
US28 patents
⚠️ This page may combine multiple inventors who share the name “WANG TSING-CHOW”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
APTOS CORP
9 patentsUS6362087B1Mar 26, 2002
Method for fabricating a microelectronic fabrication having formed therein a redistribution structure
APTOS CORP289 citations97
US6674173B1Jan 6, 2004
Stacked paired die package and method of making the same
APTOS CORP26 citations92
US6448171B1Sep 10, 2002
Microelectronic fabrication having formed therein terminal electrode structure providing enhanced passivation and enhanced bondability
APTOS CORP43 citations92
US6424037B1Jul 23, 2002
Process to make a tall solder ball by placing a eutectic solder ball on top of a high lead solder ball
APTOS CORP39 citations92
US6316831B1Nov 13, 2001
Microelectronic fabrication having formed therein terminal electrode structure providing enhanced barrier properties
APTOS CORP28 citations92
US6281041B1Aug 28, 2001
Process to make a tall solder ball by placing a eutectic solder ball on top of a high lead solder ball
APTOS CORP18 citations92
US6784089B2Aug 31, 2004
Flat-top bumping structure and preparation method
APTOS CORP18 citations80
US6544878B2Apr 8, 2003
Microelectronic fabrication having formed therein terminal electrode structure providing enhanced barrier properties
APTOS CORP9 citations74
US6635585B1Oct 21, 2003
Method for forming patterned polyimide layer
APTOS CORP12 citations70
SPERRY CORP
7 patentsUS4509146AApr 2, 1985
High density Josephson junction memory circuit
SPERRY CORP85 citations96
US4559459ADec 17, 1985
High gain non-linear threshold input Josephson junction logic circuit
SPERRY CORP7 citations73
US4501975AFeb 26, 1985
Josephson junction latch circuit
SPERRY CORP20 citations73
US4458160AJul 3, 1984
High gain Josephson junction voltage amplifier
SPERRY CORP9 citations73
US4413196ANov 1, 1983
Three Josephson junction direct coupled isolation circuit
SPERRY CORP7 citations73
US4437227AMar 20, 1984
Method of making improved tunnel barriers for superconducting Josephson junction devices
SPERRY CORP17 citations71
US4413197ANov 1, 1983
Four Josephson junction direct-coupled and gate circuit
SPERRY CORP6 citations62
SEMICONDUCTOR MFG INT SHANGHAI
6 patentsUS7053490B1May 30, 2006
Planar bond pad design and method of making the same
SEMICONDUCTOR MFG INT SHANGHAI8 citations74
US7875505B2Jan 25, 2011
Multi-die semiconductor package structure and method for manufacturing the same
SEMICONDUCTOR MFG INT SHANGHAI5 citations63
US7816787B2Oct 19, 2010
Method of forming low stress multi-layer metallurgical structures and high reliable lead free solder termination electrodes
SEMICONDUCTOR MFG INT SHANGHAI3 citations63
US7462556B2Dec 9, 2008
Method of forming low stress multi-layer metallurgical structures and high reliable lead free solder termination electrodes
SEMICONDUCTOR MFG INT SHANGHAI5 citations63
US7381636B2Jun 3, 2008
Planar bond pad design and method of making the same
SEMICONDUCTOR MFG INT SHANGHAI3 citations63
US7838411B2Nov 23, 2010
Fluxless reflow process for bump formation
SEMICONDUCTOR MFG INT SHANGHAI0 citations50
VLSI TECHNOLOGY INC
3 patentsUS5414299AMay 9, 1995
Semi-conductor device interconnect package assembly for improved package performance
VLSI TECHNOLOGY INC250 citations99
US5386141AJan 31, 1995
Leadframe having one or more power/ground planes without vias
VLSI TECHNOLOGY INC67 citations96
US5171712ADec 15, 1992
Method of constructing termination electrodes on yielded semiconductor die by visibly aligning the die pads through a transparent substrate
VLSI TECHNOLOGY INC40 citations92