US6424037B1ExpiredUtilityA1

Process to make a tall solder ball by placing a eutectic solder ball on top of a high lead solder ball

90
Assignee: APTOS CORPPriority: Nov 30, 1999Filed: Aug 28, 2001Granted: Jul 23, 2002
Est. expiryNov 30, 2019(expired)· nominal 20-yr term from priority
H05K 2203/0315H05K 2201/2081H05K 2201/1025H05K 2201/0379H10W 72/9415H10W 72/07236H10W 72/952H10W 72/255H10W 72/252H10W 72/223H10W 72/222H10W 72/90H10W 90/701H10W 72/012H10W 70/093H10W 72/20H05K 3/3436Y02P70/50
90
PatentIndex Score
39
Cited by
10
References
6
Claims

Abstract

Within a method for forming a solder interconnection structure for use within a microelectronic fabrication, there is first provided a substrate having formed thereover a bond pad. There is then formed upon the bond pad a first solder interconnection layer. There is then formed over the first solder interconnection layer an annular solder non-wettable copper oxide layer which does not cover an upper dome portion of the first solder interconnection layer. There is then formed over the upper dome portion of the first solder interconnection layer and not upon the annular solder non-wettable copper oxide layer a second solder interconnection layer.

Claims

exact text as granted — not AI-modified
What is claimed is:  
     
       1. A solder interconnection structure comprising: 
       a substrate;  
       a bond pad formed over the substrate;  
       a first solder interconnection layer formed upon the bond pad;  
       an annular copper oxide layer formed over the first solder interconnection layer but not covering an upper dome portion of the first solder interconnection layer; and  
       a second solder interconnection layer formed over the first solder interconnection layer but not upon the annular copper oxide layer.  
     
     
       2. The solder interconnection structure of  claim 1  wherein the substrate is employed within a microelectronic fabrication selected from the group consisting of integrated circuit microelectronic fabrications, organic substrate microelectronic fabrications, hybrid circuit microelectronic fabrications, ceramic substrate microelectronic fabrications, solar cell optoelectronic microelectronic fabrications, sensor image array optoelectronic microelectronic fabrications and display image array optoelectronic microelectronic fabrications. 
     
     
       3. The solder interconnection structure of  claim 1  wherein: 
       the first solder interconnection layer is formed to a thickness of from about 50 to about 150 microns; and  
       the second solder interconnection layer is formed to a thickness of from about 50 to about 125 microns.  
     
     
       4. The solder interconnection structure of  claim 1  wherein the annular copper oxide layer is formed to a thickness of from about 50 to about 200 angstroms. 
     
     
       5. The solder interconnection structure of  claim 1  wherein the first solder interconnection layer is formed of a first solder material having a lower melting point than a second solder material from which is formed the second solder interconnection layer. 
     
     
       6. The solder interconnection structure of  claim 1  wherein the first solder interconnection layer has a truncated spherical shape.

Cited by (0)

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References (0)

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