Inventor · disambiguated record
Tsing-Chow Wang
Also filed as: WANG TSING CHOW
28 granted patents·3 pending applications·1,065 citations·filing 1981–2014
97Inventor score
Files withAPTOS CORP9SEMICONDUCTOR MFG INT SHANGHAI9SPERRY CORP7VLSI TECHNOLOGY INC3HUANG YUN CHENG1
Top patents by PatentIndex Score
31 records- 0196US6362087B1Method for fabricating a microelectronic fabrication having formed therein a redistribution structureAPTOS CORP·Filed 2000·Granted Mar 26, 2002·289 cites·15 claims
- 0296US5414299ASemi-conductor device interconnect package assembly for improved package performanceVLSI TECHNOLOGY INC·Filed 1993·Granted May 9, 1995·250 cites·27 claims
- 0395US4509146AHigh density Josephson junction memory circuitSPERRY CORP·Filed 1982·Granted Apr 2, 1985·85 cites·14 claims
- 0490US6424037B1Process to make a tall solder ball by placing a eutectic solder ball on top of a high lead solder ballAPTOS CORP·Filed 2001·Granted Jul 23, 2002·39 cites·6 claims
- 0584US6448171B1Microelectronic fabrication having formed therein terminal electrode structure providing enhanced passivation and enhanced bondabilityAPTOS CORP·Filed 2000·Granted Sep 10, 2002·43 cites·11 claims
- 0682US6316831B1Microelectronic fabrication having formed therein terminal electrode structure providing enhanced barrier propertiesAPTOS CORP·Filed 2000·Granted Nov 13, 2001·28 cites·14 claims
- 0780US7053490B1Planar bond pad design and method of making the sameSEMICONDUCTOR MFG INT SHANGHAI·Filed 2005·Granted May 30, 2006·8 cites·14 claims
- 0880US5386141ALeadframe having one or more power/ground planes without viasVLSI TECHNOLOGY INC·Filed 1992·Granted Jan 31, 1995·67 cites·18 claims
- 0977US6674173B1Stacked paired die package and method of making the sameAPTOS CORP·Filed 2003·Granted Jan 6, 2004·26 cites·34 claims
- 1075US5171712AMethod of constructing termination electrodes on yielded semiconductor die by visibly aligning the die pads through a transparent substrateVLSI TECHNOLOGY INC·Filed 1991·Granted Dec 15, 1992·40 cites·16 claims
- 1175US4501975AJosephson junction latch circuitSPERRY CORP·Filed 1982·Granted Feb 26, 1985·20 cites·5 claims
- 1273US7875505B2Multi-die semiconductor package structure and method for manufacturing the sameSEMICONDUCTOR MFG INT SHANGHAI·Filed 2007·Granted Jan 25, 2011·5 cites·7 claims
- 1373US7462556B2Method of forming low stress multi-layer metallurgical structures and high reliable lead free solder termination electrodesSEMICONDUCTOR MFG INT SHANGHAI·Filed 2005·Granted Dec 9, 2008·5 cites·14 claims
- 1472US8721194B2Optical transceiver moduleHUANG YUN-CHENG·Filed 2012·Granted May 13, 2014·5 cites·8 claims
- 1568US7816787B2Method of forming low stress multi-layer metallurgical structures and high reliable lead free solder termination electrodesSEMICONDUCTOR MFG INT SHANGHAI·Filed 2008·Granted Oct 19, 2010·3 cites·12 claims
- 1668US7381636B2Planar bond pad design and method of making the sameSEMICONDUCTOR MFG INT SHANGHAI·Filed 2006·Granted Jun 3, 2008·3 cites·9 claims
- 1768US6784089B2Flat-top bumping structure and preparation methodAPTOS CORP·Filed 2003·Granted Aug 31, 2004·18 cites·28 claims
- 1868US5587336ABump formation on yielded semiconductor diesVLSI TECHNOLOGY·Filed 1994·Granted Dec 24, 1996·46 cites·3 claims
- 1967US6635585B1Method for forming patterned polyimide layerAPTOS CORP·Filed 2000·Granted Oct 21, 2003·12 cites·14 claims
- 2063US6544878B2Microelectronic fabrication having formed therein terminal electrode structure providing enhanced barrier propertiesAPTOS CORP·Filed 2001·Granted Apr 8, 2003·9 cites·12 claims
- 2162US6281041B1Process to make a tall solder ball by placing a eutectic solder ball on top of a high lead solder ballAPTOS CORP·Filed 1999·Granted Aug 28, 2001·18 cites·12 claims
- 2256US4437227AMethod of making improved tunnel barriers for superconducting Josephson junction devicesSPERRY CORP·Filed 1982·Granted Mar 20, 1984·17 cites·14 claims
- 2353US2009289337A1Lead FrameSEMICONDUCTOR MFG INT SHANGHAI·Filed 2009·Application pending·0 cites
- 2450US2008157307A1Lead frameSEMICONDUCTOR MFG INT SHANGHAI·Filed 2007·Application pending·0 cites
- 2549US4559459AHigh gain non-linear threshold input Josephson junction logic circuitSPERRY CORP·Filed 1983·Granted Dec 17, 1985·7 cites·9 claims
- 2644US7838411B2Fluxless reflow process for bump formationSEMICONDUCTOR MFG INT SHANGHAI·Filed 2007·Granted Nov 23, 2010·0 cites·30 claims
- 2744US4458160AHigh gain Josephson junction voltage amplifierSPERRY CORP·Filed 1981·Granted Jul 3, 1984·9 cites·9 claims
- 2842US2008153240A1Method for Fabricating Semiconductor DeviceSEMICONDUCTOR MFG INT SHANGHAI·Filed 2007·Application pending·0 cites
- 2941US9129883B2Package structure of optical transceiver componentLUXNET CORP·Filed 2014·Granted Sep 8, 2015·0 cites·9 claims
- 3040US4413196AThree Josephson junction direct coupled isolation circuitSPERRY CORP·Filed 1981·Granted Nov 1, 1983·7 cites·11 claims
- 3138US4413197AFour Josephson junction direct-coupled and gate circuitSPERRY CORP·Filed 1981·Granted Nov 1, 1983·6 cites·8 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →