Inventor

FULLER NICHOLAS C

US23 patents

⚠️ This page may combine multiple inventors who share the name “FULLER NICHOLAS C”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

FULLER NICHOLAS C

IBM

Interconnect structures with fully aligned vias

Adopting feature of buried electrically conductive layer in dielectrics for electrical anti-fuse application

Trilayer resist scheme for gate etching applications

Interconnect structures with fully aligned vias

Dynamic tuning of memory in MapReduce systems

Dual damascene process flow enabling minimal ULK film modification and enhanced stack integrity

De-fluorination after via etch to preserve passivation

Interconnect structures with fully aligned vias

Dynamic resource allocation in MapReduce

Enabling dynamic job configuration in mapreduce

Mixed lithography with dual resist and a single pattern transfer

System and method for plasma induced modification and improvement of critical dimension uniformity

Adopting feature of buried electrically conductive layer in dielectrics for electrical anti-fuse application

Interconnect structures with fully aligned vias

Enhanced via fill material and processing for dual damscene integration

System and method for plasma induced modification and improvement of critical dimension uniformity

FULLER NICHOLAS C

Trilayer resist scheme for gate etching applications

Methodology for fabricating isotropically recessed source and drain regions of CMOS transistors

Methodology for fabricating isotropically recessed source and drain regions of CMOS transistors

Methodology for fabricating isotropically recessed drain regions of CMOS transistors

Mixed lithography with dual resist and a single pattern transfer

YANG CHIH-CHAO

Adopting feature of buried electrically conductive layer in dielectrics for electrical anti-fuse application

BABICH KATHERINA E

Self-aligned borderless contacts for high density electronic and memory device integration