Inventor

LEI MING-TA

TW58 patents

⚠️ This page may combine multiple inventors who share the name “LEI MING-TA”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

LEI MING-TA

TAIWAN SEMICONDUCTOR MFG CO LTD

Semiconductor device and method for forming the same

Sensor in an internet-of-things

Field plate structure to enhance transistor breakdown voltage

Manufacturing method of sensor in an internet-of-things

Field plate structure to enhance transistor breakdown voltage

Plate design to decrease noise in semiconductor devices

Plate design to decrease noise in semiconductor devices

Sensor in an internet-of-things and manufacturing method of the same

Semiconductor device and method for manufacturing the same

Semiconductor device and method for manufacturing the same

Integrated chip including a device with a reduced surface field region

Field plate structure to enhance transistor breakdown voltage

Method of forming a transistor device with a gate structure having a pair of recess regions and a resistive protection layer within

Breakdown voltage capability of high voltage device

Method for forming an IC including a varactor with reduced surface field region

Plate design to decrease noise in semiconductor devices

Semiconductor device

Breakdown voltage capability of high voltage device

Reduced surface field layer in varactor

Plate design to decrease noise in semiconductor devices

Integrated circuit for high-voltage device protection

Transistor structure

Transistor device with a gate structure having recesses overlying an interface between isolation and device regions

Selective polysilicon doping for gate induced drain leakage improvement

TAIWAN SEMICONDUCTOR MFG

Method for multiple spacer width control

Salicide field effect transistors with improved borderless contact structures and a method of fabrication

Salicide field effect transistors with improved borderless contact structures and a method of fabrication

Semiconductor bonding pad structure

Selective spacer layer deposition method for forming spacers with different widths

Method for forming a semiconductor device having high-K gate dielectric material

Surface treated low-k dielectric as diffusion barrier for copper metallization

Surface treatment of metal interconnect lines

Predictions of leakage modes in integrated circuits

Method of solving contact oblique problems of an ILD layer using a rapid thermal anneal

MEGIC CORP

Low fabrication cost, high performance, high reliability chip scale package

Post passivation metal scheme for high-performance integrated circuit devices

Method of making a low fabrication cost, high performance, high reliability chip scale package

Post passivation metal scheme for high-performance integrated circuit devices

Reliable metal bumps on top of I/O pads after removal of test probe marks

MEGICA CORP

Structure and manufacturing method of a chip scale package with low fabrication cost, fine pitch and high reliability solder bump

Reliable metal bumps on top of I/O pads after removal of test probe marks

Low fabrication cost, high performance, high reliability chip scale package

Low fabrication cost, high performance, high reliability chip scale package

LEE JIN-YUAN

Low fabrication cost, high performance, high reliability chip scale package

Low fabrication cost, high performance, high reliability chip scale package

Low fabrication cost, high performance, high reliability chip scale package

LIN MOU-SHIUNG

Structure and manufacturing method of a chip scale package

Post passivation metal scheme for high-performance integrated circuit devices

TSAI WEN-CHI

Semiconductor device and method for forming the same

HUANG CHING-CHENG

Reliable metal bumps on top of I/O pads after removal of test probe marks