Semiconductor device

Abstract

A semiconductor device includes a semiconductor substrate, a gate dielectric, a gate electrode, and a pair of source/drain regions. The gate dielectric is disposed in the semiconductor substrate having an upper boundary lower than an upper surface of the semiconductor substrate, and an upper surface flush with the upper surface of the semiconductor substrate. The gate electrode is disposed over the gate dielectric having a first section over the upper boundary of the gate dielectric and a second section over the upper surface of the gate dielectric. The second section partially covers and partially exposes the upper surface of the gate dielectric. The pair of source/drain regions are disposed on opposing sides of the gate dielectric.

What is claimed is: 
     
       1. A semiconductor device, comprising:
 a semiconductor substrate; 
 a gate dielectric in the semiconductor substrate having an upper boundary lower than an upper surface of the semiconductor substrate, and an upper surface flush with the upper surface of the semiconductor substrate; 
 a gate electrode disposed over the gate dielectric having a first section over the upper boundary of the gate dielectric and a second section over the upper surface of the gate dielectric, wherein the second section partially covers and partially exposes the upper surface of the gate dielectric; and 
 a pair of source/drain regions on opposing sides of the gate dielectric. 
 
     
     
       2. The semiconductor device of  claim 1 , further comprising a pair of well regions in the semiconductor substrate and under the pair of source/drain regions, respectively. 
     
     
       3. The semiconductor device of  claim 2 , wherein one of the pair of well regions is smaller and shallower than another one of the pair of well regions. 
     
     
       4. The semiconductor device of  claim 2 , wherein the pair of well regions have different doping concentrations. 
     
     
       5. The semiconductor device of  claim 2 , wherein a doping type of the pair of well regions is the same as that of the pair of source/drain regions. 
     
     
       6. The semiconductor device of  claim 2 , wherein doping concentrations of the pair of well regions is lower than that of the pair of source/drain regions. 
     
     
       7. The semiconductor device of  claim 1 , further comprising a deep well region formed in the semiconductor substrate. 
     
     
       8. The semiconductor device of  claim 1 , further comprising an isolation structure in the semiconductor substrate. 
     
     
       9. The semiconductor device of  claim 8 , wherein a depth of the gate dielectric is substantially the same with that of the isolation structure. 
     
     
       10. The semiconductor device of  claim 1 , wherein an upper surface of the gate electrode is lower than the upper surface of the semiconductor substrate. 
     
     
       11. A semiconductor device, comprising:
 a semiconductor substrate; 
 a first semiconductor device, comprising:
 a first gate dielectric in the semiconductor substrate having an upper surface flush with an upper surface of the semiconductor substrate; 
 a first gate electrode disposed over the first gate dielectric, wherein the first gate electrode partially covers and partially exposes the upper surface of the first gate dielectric; and 
 a pair of first source/drain regions on opposing sides of the first gate dielectric; and 
 
 a second semiconductor device, comprising:
 a second gate dielectric over the semiconductor substrate having an upper surface higher than the upper surface of the semiconductor substrate; 
 a second gate electrode disposed over the second gate dielectric; and 
 a pair of second source/drain regions on opposing sides of the second gate dielectric. 
 
 
     
     
       12. The semiconductor device of  claim 11 , wherein the second gate electrode entirely covers the upper surface of the second gate dielectric. 
     
     
       13. The semiconductor device of  claim 11 . wherein the first semiconductor device further comprises a pair of first spacers on opposing sides of the first gate electrode. 
     
     
       14. The semiconductor device of  claim 13 , wherein the pair of first spacers are in contact with the upper surface of the first gate dielectric. 
     
     
       15. The semiconductor device of  claim 11 , wherein a thickness of the first gate dielectric is greater than a thickness of the second gate dielectric. 
     
     
       16. The semiconductor device of  claim 11 , wherein an upper surface of the first gate electrode is substantially flush with an upper surface of the second gate electrode. 
     
     
       17. A semiconductor device, comprising:
 a semiconductor substrate; 
 a gate dielectric in the semiconductor substrate having a concave profile that defines an upper boundary lower than an upper surface of the semiconductor substrate; 
 a gate electrode disposed over the gate dielectric; 
 a pair of source/drain regions on opposing sides of the gate dielectric; and 
 an inter-layer dielectric covering the gate electrode, wherein a thickness of the inter-layer dielectric is smaller than a sum of a thickness of the gate dielectric and a thickness of the gate electrode. 
 
     
     
       18. The semiconductor device of  claim 17 , wherein an upper surface of the gate dielectric is substantially flush with a bottom surface of the inter-layer dielectric. 
     
     
       19. The semiconductor device of  claim 17 , further comprising a pair of spacers on opposing sides of the gate electrode, wherein the pair of spacers are in contact with an upper surface of the gate dielectric. 
     
     
       20. The semiconductor device of  claim 17 , wherein the gate electrode partially covers and partially exposes an upper surface of the gate dielectric.