Inventor

BHAKTA JAYESH R

US66 patents

⚠️ This page may combine multiple inventors who share the name “BHAKTA JAYESH R”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

BHAKTA JAYESH R

NETLIST INC

Circuit providing load isolation and memory domain translation for memory module

Circuit providing load isolation and memory domain translation for memory module

Memory module decoder

Memory module with a circuit providing load isolation and memory domain translation

Memory module decoder

Memory module with a circuit providing load isolation and memory domain translation

Memory module decoder

Apparatus and method for self-test in a multi-rank memory module

Memory board with self-testing capability

Memory board with self-testing capability

Module having at least two surfaces and at least one thermally conductive layer therebetween

Circuit with flexible portion

High density module having at least two substrates and at least one thermally conductive layer therebetween

Circuit card with flexible connection for memory module with heat spreader

High density memory module using stacked printed circuit boards

High density memory module using stacked printed circuit boards

Arrangement of integrated circuits in a memory module

Arrangement of integrated circuits in a memory module

Arrangement of integrated circuits in a memory module

Arrangement of integrated circuits in a memory module

Module having at least two surfaces and at least one thermally conductive layer therebetween

Circuit with flexible portion

High-density memory module utilizing low-density memory components

Memory module with data buffering

Memory module with distributed data buffers and method of operation

Memory module with distributed data buffers and method of operation

Electronic module with flexible portion

Memory module with load reducing circuit and method of operation

Memory module with local synchronization and method of operation

Memory module with data buffering

Memory module with distributed data buffers

Memory module with controlled byte-wise buffers

Memory module with timing-controlled data buffering

Memory module with local synchronization

Memory module with timing-controlled data paths in distributed data buffers

Arrangement of memory devices in a multi-rank memory module

Multi-mode memory module with data handlers

LEE HYUN

System and method utilizing distributed byte-wise buffers on a memory module

System and method of increasing addressable memory space on a memory board

Systems and methods for refreshing a memory module

Circuit providing load isolation and noise reduction

Circuit providing load isolation and noise reduction

BHAKTA JAYESH R

Multirank DDR memory modual with load reduction

Circuit for providing chip-select signals to a plurality of ranks of a DDR memory module

Circuit for providing chip-select signals to a plurality of ranks of a DDR memory module

Circuit with flexible portion

SOLOMON JEFFREY C

Circuit for memory module

Circuit for memory module

Circuit providing load isolation and memory domain translation for memory module

VIKING COMPONENTS

High-density computer module with stacked parallel-plane packaging