Inventor

YOON SEI SEUNG

US103 patents

⚠️ This page may combine multiple inventors who share the name “YOON SEI SEUNG”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

YOON SEI SEUNG

QUALCOMM INC

Wide range multiport bitcell

Bit line voltage control in spin transfer torque magnetoresistive random access memory

Write driver for memory

Write word-line assist circuitry for a byte-writeable memory

MRAM device with shared source line

Controlled value reference signal of resistance based memory circuit

Spin transfer torque magnetoresistive random access memory and design methods

Word line transistor strength control for read and write in spin transfer torque magnetoresistive random access memory

Flexible power sequencing for dual-power memory

Hybrid ternary content addressable memory

Process variation tolerant memory design

Adapting word line pulse widths in memory systems

Memory device with configurable delay tracking

CMOS level shifter circuit design

Memory cell with improved write margin

Read/write assist for memories

Weak keeper circuit for memory device

Read disturb reduction circuit for spin transfer torque magnetoresistive random access memory

In-situ resistance measurement for magnetic random access memory (MRAM)

High frequency pseudo dual port memory

System and method for reducing programming voltage stress on memory cell devices

SAMSUNG ELECTRONICS CO LTD

Integrated circuit memory devices having cross-coupled isolation gate controllers which provide simultaneous reading and writing capability to multiple memory arrays

Semiconductor memory using low power supply voltage

Internal clock signal delay circuit and method for delaying internal clock signal in semiconductor device

Multi-bank memory devices having common standby voltage generator for powering a plurality of memory array banks in response to memory array bank enable signals

Voltage boosting circuits having backup voltage boosting capability

Sense amplifier circuit in semiconductor memory device

Semiconductor memory device having self-refresh and back-bias circuitry

Integrated circuit devices having improved internal voltage generators which reduce timing skew in buffer circuits therein

Integrated circuits including voltage-controllable power supply systems that can be used for low supply voltage margin testing and related methods

Integrated power supply voltage generators having reduced susceptibility to parasitic latch-up during set-up mode operation

Method and apparatus for controlling column select lines in a synchronous memory device

MICRON TECHNOLOGY INC

Open digit line array architecture for a memory array

Open digit line array architecture for a memory array

Open digit line array architecture for a memory array

Open digit line array architecture for a memory array

T RAM INC

Bit line control and sense amplification for TCCT-based memory cells

Single data line sensing scheme for TCCT-based memory cells

Circuit and method for implementing a write operation with TCCT-based memory cells

Bit line control and sense amplification for TCCT-based memory cells

YOON SEI SEUNG

Word line voltage control in STT-MRAM

Data integrity preservation in spin transfer torque magnetoresistive random access memory

JUNG SEONG-OOK

Write operation for spin transfer torque magnetoresistive random access memory with reduced bit cell size

KANG SEUNG H

Magnetic element utilizing protective sidewall passivation

T RAM SEMICONDUCTOR INC

Single data line sensing scheme for TCCT-based memory cells

SAMSUNG ELECTRIC

Voltage pumping circuit for semiconductor memory device

CHO SUNG IL

System and method of operating a memory device

ABU RAHMA MOHAMED H

Memory read stability using selective precharge

PARK DONGKYU

Dual power scheme in memory circuit

ABU-RAHMA MOHAMED HASSAN

System and method to read and write data a magnetic tunnel junction element