Inventor

BRYG WILLIAM R

US38 patents

⚠️ This page may combine multiple inventors who share the name “BRYG WILLIAM R”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

BRYG WILLIAM R

HEWLETT PACKARD CO

Computer memory address control apparatus utilizing hashed address tags in page tables which are compared to a combined address tag and index which are longer than the basic data width of the associated computer

Privilege level checking instruction for implementing a secure hierarchical computer system

Cache memory consistency control with explicit software instructions

Apparatus and method for a virtual hashed page table

Partial cache line write transactions in a computing system with a write back cache

Multiprocessor system for maintaining cache coherency by checking the coherency in the order of the transactions being issued on the bus

Method and apparatus for checking cache coherency in a computer architecture

Method for decreasing time penalty resulting from a cache miss in a multi-level cache system

Access hints for input/output address translation mechanisms

Cache memory with variable fetch and replacement schemes

Direct input/output in a virtual memory system

Queue-based predictive flow control mechanism with indirect determination of queue fullness

Queue-based predictive flow control mechanism

Forming linked lists using content addressable memory

Multiple arbitration scheme

Flexible N-way memory interleaving

Cache tag lookaside

Method and means for moving bytes in a reduced instruction set computer

Coherence index generation for use by an input/output adapter located outside of the processor to detect whether the updated version of data resides within the cache

Computer that selectively forces ordered execution of store and load operations between a CPU and a shared memory

Explicit instructions for control of translation lookaside buffers

Translation mechanism for input/output addresses

Fast pipelined distributed arbitration scheme

Method and apparatus for ensuring data consistency between an i/o channel and a processor

Atomic operation control scheme

Software method for implementing dismissible instructions on a computer

INST THE DEV OF EMERGING ARCHI

Method and apparatus for calculating a page table index from a virtual address

Apparatus and method for a load bias--load with intent to semaphore

Page table walker that uses at least one of a default page size and a page size selected for a virtual address space to position a sliding field in a virtual address

Apparatus and method for a virtual hashed page table

Method and apparatus for instruction and data serialization in a computer processor

Method and apparatus for pre-validating regions in a virtual addressing scheme

Method and apparatus for pre-validating regions in a virtual addressing scheme

HEWLETT PACKARD DEVELOPMENT CO

Forming linked lists using content addressable memory

System and method for memory interleaving using cell map with entry grouping for higher-way interleaving

System and method for memory migration in distributed-memory multi-processor systems

INTEL CORP

Method and apparatus for transferring data in a computer system

Software and hardware-managed translation lookaside buffer