Computer that selectively forces ordered execution of store and load operations between a CPU and a shared memory

Abstract

A computer apparatus which detects a store or load operation into or from a shared memory page by a program that does not provide for synchronization when executed by a CPU that completes instructions out of program order. After the store or load is detected, the CPU explicitly orders operations into the shared memory page. Store operations are ordered such that no new store into the shared memory page is performed until all prior store operations into the shared memory page are complete. Also, load operations are ordered such that load operations from the shared memory page are performed in program order. This ordering is achieved by maintaining a process bit and a memory attribute bit associated with a shared memory page. When both bits are true, all load or store operations referencing the shared memory page are ordered.

We claim: 
     
       1. A digital computer having a central processing unit (CPU) that executes computer instructions associated with a computer program, including load and store instructions, wherein the computer instructions are in a program order, comprising: a control system operative to control the CPU as follows: if a first load instruction being executed by the CPU references a shared memory area used for inter-process communication with either another program or another CPU, and a process status bit associated with the CPU has a particular value indicating that load instructions accessing the shared memory area and associated with the program must be ordered, the control system controls the CPU such that a second load operation requested by a second load instruction that accesses the shared memory area and is subsequent to the first load instruction in the program order is not completed prior to a first load operation requested by the first load instruction being completed, while allowing other instructions subsequent to the first load instruction in the program order to execute before the first load operation is completed; or   if a second store instruction being executed by the CPU references a shared memory area used for inter-process communication with either another program or another CPU, and a process status bit associated with the CPU has a particular value indicating that store instructions accessing the shared memory area and associated with the program must be ordered, the control system controls the CPU such that a second store operation requested by the second store instruction is not completed until a first store operation requested by a first store instruction that accesses the shared memory area and precedes the second store instruction in the program order has completed, while the second store operation is allowed to complete before other instructions that precede the second store instruction in the program order.     
     
     
       2. A digital computer as in claim 1 wherein the control system detects a reference to a shared memory area by checking that a memory attribute bit, associated with the referenced memory area, has a particular value. 
     
     
       3. A digital computer as in claim 2 wherein the memory attribute bit is stored in a translation lookaside buffer. 
     
     
       4. A digital computer as in claim 1 wherein the process status bit is stored in a CPU register. 
     
     
       5. A digital computer having a central processing unit (CPU) that executes computer instructions associated with a computer program, including load and store instructions, wherein the instructions are in a program order, comprising: a control system operative to control the CPU as follows: if a first load instruction being executed by the CPU references a shared memory area used for inter-process communication with either another program or another CPU, and a process status bit associated with the CPU has a particular value indicating that load instructions accessing the shared memory area and associated with the program must be ordered, the control system controls the CPU such that a second load operation requested by a second load instruction that accesses the shared memory area and is subsequent to the first load instruction in the program order is not completed prior to a first load operation requested by the first load instruction being completed, and no store operation requested by a store instruction that is subsequent to the first load instruction in the program order and references the shared memory area is completed until the first load instruction is completed, while allowing other instructions subsequent to the first load instruction in the program order to execute before the first load operation is completed; or   if a second store instruction being executed by the CPU references a shared memory area used for inter-process communication with either another program or another CPU, and a process status bit associated with the CPU has a particular value indicating that store instructions accessing the shared memory area and associated with the program must be ordered, the control system controls the CPU such that a second store operation requested by the second store instruction is not completed until a first store operation requested by a first store instruction that accesses the shared memory area and precedes the second store instruction in program order has completed, and the second store operation requested by the second store instruction is not completed until all load operations requested by load instructions that reference the shared memory area and precede the second store operation in program order are completed, while the second store operation is allowed to complete before other instructions that precede the second store instruction in the program order.     
     
     
       6. A digital computer as in claim 5 wherein the control system detects a reference to a shared memory area by checking that a memory attribute bit, associated with the referenced memory area, has a particular value. 
     
     
       7. A digital computer as in claim 6 wherein the memory attribute bit is stored in a translation lookaside buffer. 
     
     
       8. A digital computer as in claim 5 wherein the process status bit is stored in a CPU register.