Inventor

CAMPARDO GIOVANNI

IT101 patents

⚠️ This page may combine multiple inventors who share the name “CAMPARDO GIOVANNI”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

CAMPARDO GIOVANNI

ST MICROELECTRONICS SRL

Method for storing and reading data in a multilevel nonvolatile memory

Row decoder for a nonvolatile memory with capability of selectively biasing word lines to positive or negative voltages

Sense amplifier circuit for semiconductor memory devices

Programmable logic arrays

Circuit structure for providing a hierarchical decoding in semiconductor memory devices

Nonvolatile memory device, having parts with different access time, reliability, and capacity

Nonvolatile multilevel memory and reading method thereof

Row decoder for a flash-EEPROM memory device with the possibility of selective erasing of a sub-group of rows of a sector

Architecture for a flash-EEPROM simultaneously readable in other sectors while erasing and/or programming one or more sectors

Method for erasing an electrically erasable nonvolatile memory device, in particular an eeprom-flash memory device, and an electrically erasable nonvolatile memory device, in particular an eeprom-flash memory device

Non-volatile memory device with row redundancy

ESD protection network for circuit structures formed in a semiconductor

Device and method for reading nonvolatile memory cells

Method and circuit for reading low-supply-voltage nonvolatile memory cells

Single-cell reference signal generating circuit for reading nonvolatile memory

Method of programming a nonvolatile flash-EEPROM memory array using source line switching transistors

Nonvolatile memory device, in particular a flash-EEPROM

Level shifter for semiconductor memory device implemented with low-voltage transistors

Semiconductor memory with embedded DRAM

Method and circuit for generating reference voltages for reading a multilevel memory cell

Nonvolatile memory device with hierarchical sector decoding

CMOS switch circuit for transferring high voltages, in particular for line decoding in nonvolatile memories, with reduced consumption during switching

Read circuit for a nonvolatile memory

Low-supply-voltage nonvolatile memory device with voltage boosting

Method of reading, erasing and programming a nonvolatile flash-EEPROM memory arrray using source line switching transistors

Method and circuit for dynamic reading of a memory cell, in particular a multi-level nonvolatile memory cell

Method and circuit for dynamic reading of a memory cell at low supply voltage and with low output dynamics

Non-volatile memory capable of autonomously executing a program

Method for reading a multilevel nonvolatile memory and multilevel nonvolatile memory

Line decoder for memory devices

Failure tolerant memory device, in particular of the flash EEPROM type

Reference signal generating method and circuit for differential evaluation of the content of nonvolatile memory cells

Nonvolatile flash-EEPROM memory array with source control transistors

Microelectromechanical device, which can be used as non-volatile memory module or relay, and memory including a plurality of microelectromechanical devices

Circuit and method for reading a memory cell of a non-volatile memory device

SGS THOMSON MICROELECTRONICS

Circuit and method for generating a read reference signal for nonvolatile memory cells

Sense amplifier having capacitively coupled input for offset compensation

EEPROM memory with contactless memory cells

EEPROM memory device with simultaneous read and write sector capabilities

Read circuit and method for nonvolatile memory cells with an equalizing structure

Output stage for a memory device and for low voltage applications

Bidirectional charge pump generating either a positive or negative voltage

Nonvolatile memory device having sectors of selectable size and number

Circuit for sensing the state of matrix cells in MOS EPROM memories including an offset current generator

SGS MICROELETTRONICA SPA

Circuital device for the power-on reset of digital integrated circuits in MOS technology

Source bias generator for natural transistors in MOS digital integrated circuits

LOSAVIO ALDO

Multi chip electronic system

TIZIANI FEDERICO

Controller to execute error correcting code algorithms and manage NAND memories

MICRON TECHNOLOGY INC

Controller to manage NAND memories

CAMPARDO GIOVANNI

Secondary memory element for non-volatile memory