Inventor

RUDECK PAUL J

US36 patents

⚠️ This page may combine multiple inventors who share the name “RUDECK PAUL J”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

RUDECK PAUL J

MICRON TECHNOLOGY INC

Minimizing adjacent wordline disturb in a memory device

Flash memory cell

Methods for fabricating an improved floating gate memory cell

Method and structure for an improved floating gate memory cell

Flash memory cell for high efficiency programming

Flash memory cell for high efficiency programming

Flash memory cell for high efficiency programming

Minimizing adjacent wordline disturb in a memory device

Minimizing adjacent wordline disturb in a memory device

Method to remove an oxide seam along gate stack edge, when nitride space formation begins with an oxide liner surrounding gate stack

Method and structure for an oxide layer overlaying an oxidation-resistant layer

Semiconductor contact device and method

Semiconductor contact device

Flash memory cell for high efficiency programming

Semiconductor contact device

Method to remove an oxide seam along gate stack edge, when nitride space formation begins with an oxide liner surrounding gate stack

Gate coupling in floating-gate memory cells

Programmable memory devices supported by semiconductor substrates

Methods and structure for an improved floating gate memory cell

Programmable memory devices supported by semiconductive substrates

Methods of forming programmable memory devices comprising tungsten

Method and structure for an improved floating gate memory cell

Flash memory cell for high efficiency programming

Flash memory cell for high efficiency programming

Flash memory cell for high efficiency programming

Modified source/drain re-oxidation method and system

Programmable memory devices supported by semiconductor substrates

Method and structure for an improved floating gate memory cell

Use of selective oxidation to form asymmetrical oxide features during the manufacture of a semiconductor device

Method and structure for an oxide layer overlying an oxidation-resistant layer

Method and structure for an improved floating gate memory cell

Use of selective oxidation to form asymmetrical oxide features during the manufacture of a semiconductor device

Modified source/drain re-oxidation method and system

Modified source/drain re-oxidation method and system

IBM

Alignment mark system for electron beam/optical mixed lithography

RUDECK PAUL J

Methods of filling isolation trenches for semiconductor devices and resulting structures