Methods for fabricating an improved floating gate memory cell

Abstract

Methods for fabricating improved floating gate memory cells are provided. A substrate and a first insulating layer are fabricated, where the first insulating layer is formed on the substrate. A shallow trench isolation (STI) region is fabricated having walls that form edges in the substrate and edges to a first conducting layer where the edges of the first conducting layer are aligned with the edges of the substrate. A second insulating layer is formed on the first conducting layer and a second conducting layer formed on the first insulating layer. The invention also includes a method that capitalizes on a single step process for defining the STI region and the floating gate for a memory cell that aligns edges formed in the substrate by the walls of the STI region with the edges of the floating gate formed by the walls of the STI region.

1. A method for fabricating a non volatile memory cell, comprising:
 forming a shallow trench isolation region having walls that form edges in a substrate and form edges in a first conducting layer wherein the edges of the first conducting layer are aligned with and perpendicular to edges of the substrate and wherein the shallow trench isolation region isolates the non volatile memory cell;  
 forming an insulating layer on the first conducting layer; and  
 forming a second conducting layer on the insulating layer.  
 
   
   
     2. The method of  claim 1  wherein in forming the insulating layer, the insulating layer includes a non uniform top surface. 
   
   
     3. The method of  claim 1  wherein in forming the second conducting layer, the first conducting layer includes a floating gate and the second conducting layer includes a control gate. 
   
   
     4. A method of fabricating a non volatile memory cell, comprising:
 forming a tunnel oxide layer on a substrate, wherein the tunnel oxide layer includes a first conducting layer and a second conducting layer;  
 forming an insulating layer on the first conducting layer having a top surface that is non uniform;  
 forming a floating gate in a shallow trench region by using a single lithographic process, wherein the shallow trench region includes walls that form edges in the substrate and form edges in the first conducting layer; and  
 fabricating the non volatile memory cell to a configurable size.  
 
   
   
     5. The method of  claim 4  wherein in forming the floating gate comprises, etching the first conductive layer, the tunnel oxide layer, and the substrate. 
   
   
     6. The method of  claim 4  wherein in forming the floating gate, the edges of the substrate and the edges of the first conducting layer are perpendicular to one another. 
   
   
     7. A method for fabricating a non volatile memory cell, comprising:
 forming a first conducting layer on a tunnel oxide layer;  
 aligning edges of the first conducting layer with edges of a substrate forming an insulating layer on the first conducting layer;  
 forming a second conducting layer on the insulating layer; and  
 fabricating the first conducting layer with a top surface that is non uniform.  
 
   
   
     8. The method of  claim 7  wherein in aligning, the edges of the first conducting layer are perpendicular to the edges of the substrate. 
   
   
     9. The method of  claim 7  further comprising, forming a shallow trench isolation region that isolates the non volatile memory cell. 
   
   
     10. A method for fabricating a non volatile memory cell, comprising:
 aligning edges of a first conducting layer with edges of a substrate forming an insulating layer on the first conducting layer, wherein the edges of the first conducting layer are perpendicular to the edges of the substrate; and  
 fabricating the first conducting layer with a top surface that is non uniform.  
 
   
   
     11. The method of  claim 10  further comprising forming a second conducting layer on the insulating layer. 
   
   
     12. The method of  claim 10  wherein in aligning, the edges of the first conducting layer and the edges of the substrate are aligned in a single lithographic process. 
   
   
     13. A method for fabricating an array of floating gate tunnel oxide (FLOTOX) transistors, comprising:
 forming a number of FLOTOX transistors, wherein forming a FLOTOX transistors comprises: 
 forming a first insulating layer on a substrate;  
 forming a floating gate on the first insulating layer having a non uniform top surface;  
 forming a shallow trench isolation region having walls that form edges in a body region of the substrate and edges to the floating gate such that the edges of the floating gate are aligned with and perpendicular to the edges of the body region and wherein the shallow trench isolation region isolates the FLOTOX transistor;  
 forming a second insulating layer on the floating gate; and  
 forming a control gate on the second insulating layer;  
 
 coupling source regions of the number of FLOTOX transistors together; and  
 wherein drain regions of the number of FLOTOX transistors are isolated from each other by the shallow trench isolation regions.  
 
   
   
     14. The method of  claim 13  wherein in forming the first insulating layer, the substrate includes a source region, a drain region, and the body region, which separates the source region and the drain region. 
   
   
     15. The method of  claim 13  wherein in forming the floating gate, the non uniform top surface has wings adjacent to the shallow trench region. 
   
   
     16. A method for fabricating a memory device comprising:
 forming a number of FLOTOX transistors, wherein forming a FLOTOX transistors comprises: 
 forming a tunnel oxide layer on a substrate, wherein the substrate includes a source region, a drain region and a body region separating the source region and the drain region;  
 forming a floating gate on the tunnel oxide layer having a non uniform top surface;  
 forming a shallow trench isolation region having walls that form edges in the body region such that the edge of the floating gate is aligned with and perpendicular to one of the edges of the body region and wherein the shallow trench isolation region isolates the FLOTOX transistor;  
 forming an insulating layer on the floating gate; and  
 forming a control gate on the insulating layer;  
 
 forming a sourceline coupled to the source region of each of the number of FLOTOX transistors; and  
 forming at least one wordline coupled to at least one control gate of the number of FLOTOX transistors.  
 
   
   
     17. The method of  claim 16  wherein in forming the number of FLOTOX transistors further comprises forming at least one of the number of FLOTOX transistors to a configurable area. 
   
   
     18. The method of  claim 16  wherein in forming the floating gate, the non uniform top surface increases a surface area of the floating gate. 
   
   
     19. A method for fabricating an array of floating gate tunnel oxide (FLOTOX) transistors comprising:
 forming a number of FLOTOX transistors, wherein forming a FLOTOX transistors comprises: 
 forming a tunnel oxide layer on a substrate having a source region and a drain region with a body region separating the source region and the drain region;  
 forming a floating gate on a first insulating layer;  
 aligning an edge of the floating gate with one edge of the body region in shallow trench that isolates the FLOTOX transistor, wherein the edges are perpendicular to one another;  
 forming a second insulating layer on the floating gate, wherein the second insulating layer includes a control gate; and  
 
 coupling the source regions of the number of FLOTOX transistors together, and wherein the drain regions of the number of FLOTOX transistors are isolated from each other by shallow trench isolation regions.  
 
   
   
     20. The method of  claim 19  wherein in aligning comprises, forming the shallow trench regions that have walls that form in the body regions. 
   
   
     21. The method of  claim 19  wherein in forming the floating gate, the floating gate includes a non uniform top surface and has wings adjacent to the floating gate's shallow trench region. 
   
   
     22. A method for fabricating a memory device comprising:
 forming a number of FLOTOX transistors, wherein forming a FLOTOX transistors comprises: 
 forming a tunnel oxide layer on a substrate having a source region and a drain with a body region separating the source region and the drain region;  
 forming a floating gate on the tunnel oxide layer with a non-uniform top surface;  
 aligning an edge of the floating gate with one edge of the body region within a shallow trench isolation region that isolates the FLOTOX transistor;  
 forming an insulating layer on the floating gate and a control gate on the insulating layer; and  
 
 forming a sourceline coupled to the source region of each of the number of FLOTOX transistors; and  
 forming at least one wordline coupled to at least one control gate of the number of FLOTOX transistors.  
 
   
   
     23. The method of  claim 22  wherein in aligning the edges are perpendicular to one another. 
   
   
     24. The method of  claim 22  wherein in forming the floating gate, the non-uniform top surface of the floating gate of at least one of the number of FLOTOX transistors includes wings adjacent to the shallow trench isolation region.