Inventor

HORNUNG BRYAN

US44 patents

⚠️ This page may combine multiple inventors who share the name “HORNUNG BRYAN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

HORNUNG BRYAN

MICRON TECHNOLOGY INC

Method of demand scrubbing by placing corrected data in memory-side cache

Method of demand scrubbing by placing corrected data in memory-side cache

Data input/output operations during loop execution in a reconfigurable compute fabric

High bandwidth gather cache

Virtual addresses for a memory system

Connectivity in coarse grained reconfigurable architecture

Mechanism to handle breakpoints in a multi-element processor

High bandwidth gather cache

Connectivity in coarse grained reconfigurable architecture

Loading data from memory during dispatch

Memory controller implemented error correction code memory

Memory controller implemented error correction code memory

Loop execution in a reconfigurable compute fabric using flow controllers for respective synchronous flows

Context load mechanism in a coarse-grained reconfigurable array processor

Context load mechanism in a coarse-grained reconfigurable array processor

Loop execution in a reconfigurable compute fabric using flow controllers for respective synchronous flows

Multiple channel memory system

Shared virtual address spaces

Method for providing logging for persistent memory

Dynamic power and thermal loading in a chiplet-based system

Indexing external memory in a reconfigurable compute fabric

Interpolation acceleration in a processor memory interface

Global virtual address space across operating system domains

Increasing cache hits for synthetic aperture radar

Methods and systems for communications between hardware components

Loop execution in a reconfigurable compute fabric

Mask field propagation among memory-compute tiles in a reconfigurable architecture

Methods and systems for communications between hardware components

HEWLETT PACKARD DEVELOPMENT CO

Method and system for achieving varying manners of memory access

System and method for mapping bus addresses to memory locations utilizing access keys and checksums

Hardware description language-embedded regular expression support for module iteration and interconnection

System and method for dynamically moving checksums to different memory locations

Using local storage to handle multiple outstanding requests in a SCI system

System and method for performing backward error recovery in a computer

System and method for building a checksum

System and method for achieving enhanced memory access capabilities

Using local storage to handle multiple outstanding requests in a SCI system

HEWLETT PACKARD CO

Global hard error distribution using the SCI interconnect

System and method for dynamically updating memory address mappings

Increment update in an SCI based system

System and method for dynamically moving checksums to different memory locations

System and method for utilizing checksums to recover data

Sharing list for multi-node DMA write operations

GILES CHRIS M

Address handling