Inventor

TSCHANZ JAMES W

US80 patents

⚠️ This page may combine multiple inventors who share the name “TSCHANZ JAMES W”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

TSCHANZ JAMES W

INTEL CORP

Temperature dependent regulation of threshold voltage

System using body-biased sleep transistors to reduce leakage power while minimizing performance penalties and noise

Adaptive body bias for clock skew compensation

Method and apparatus to clamp SRAM supply voltage

Wide-range local bias generator for body bias grid

Bitcell state retention

Graphics processor sub-domain voltage regulation

Method and apparatus to clamp SRAM supply voltage

Reducing power consumption in integrated circuits

Flip-flop circuit having dual-edge triggered pulse generator

Reducing leakage currents in integrated circuits

Frequency management apparatus, systems, and methods

Bias generator for body bias

Method and apparatus for reducing power consumption through dynamic control of supply voltage and body bias including maintaining a substantially constant operating frequency

Transmission-gate based flip-flop

Physically unclonable function circuit including memory elements

Physically unclonable function circuit using resistive memory device

Component reliability budgeting system

Apparatus for power consumption reduction

Method, apparatus and system of adjusting one or more performance-related parameters of a processor

Gating for dual edge-triggered clocking

Processor apparatus with body bias circuitry to delay thermal throttling

Silicon on insulator device design having improved floating body effect

Delay fault detection using latch with error sampling

Method and apparatus for applying body bias to integrated circuit die

Dual loop digital low drop regulator and current sharing control apparatus for distributable voltage regulators

Voltage level shifter circuit

Adaptive microphone sampling rate techniques

Apparatus to reduce retention failure in complementary resistive memory

Component reliability budgeting system

Majority voter apparatus, systems, and methods

Time-borrowing N-only clocked cycle latch

Skewed repeater bus

Graphics processor sub-domain voltage regulation

Digitally phase locked low dropout regulator apparatus and system using ring oscillators

Apparatus to reduce retention failure in complementary resistive memory

Digital clamp for state retention

Bitcell state retention

Apparatus for reducing write minimum supply voltage for memory

Encryption code generation using spin-torque NANO-oscillators

Method for power consumption reduction

Sequential circuit with error detection

Apparatus and method for detecting or repairing minimum delay errors

KULKARNI JAYDEEP P

Apparatus for reducing write minimum supply voltage for memory

Circuits and methods for memory

RAYCHOWDHURY ARIJIT

Low power voice detection

Multi-supply sequential logic unit

NARENDRA SIVA G

Power management integrated circuit

BOWMAN KEITH A

Self-contained, path-level aging monitor apparatus and method

MEINERZHAGEN PASCAL A

Apparatus for dual purpose charge pump