Inventor

LOJEK BOHUMIL

US43 patents

⚠️ This page may combine multiple inventors who share the name “LOJEK BOHUMIL”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

LOJEK BOHUMIL

ATMEL CORP

Vertical gate CMOS with lithography-independent gate length

Charge trapping nanocrystal dielectric for non-volatile memory transistor

Non-volatile memory array with simultaneous write and erase feature

Fowler-Nordheim block alterable EEPROM memory cell

Multi-level memory cell with lateral floating spacers

Nanocrystal electron device

Method of fabricating a self-aligned non-volatile memory cell

Eeprom cell with asymmetric thin window

Memory cell with reduced size and standby current

Low voltage non-volatile memory cells using twin bit line current sensing

Twin EEPROM memory transistors with subsurface stepped floating gates

Mirror image non-volatile memory cell transistor pairs with single poly layer

Ultra small thin windows in floating gate transistors defined by lost nitride spacers

Self-aligned nanometer-level transistor defined without lithography

Non-volatile nanocrystal memory transistors using low voltage impact ionization

Mirror image memory cell transistor pairs featuring poly floating spacers

Mirror image memory cell transistor pairs featuring poly floating spacers

Method of making nonvolatile transistor pairs with shared control gate

Method of making an EEPROM cell with asymmetric thin window

Self-aligned non-volatile memory cell

Method of fabricating a self-aligned non-volatile memory cell

Non-thermal annealing with electromagnetic radiation in the terahertz range of doped semiconductor material

Method of preventing shift of alignment marks during rapid thermal processing

Method of making EEPROM transistor pairs for block alterable memory

Method of fabricating a semiconductor device having a toroidal-like junction

Semiconductor device with a toroidal-like junction

Multi-bit nanocrystal memory

Lithography-independent fabrication of small openings for forming vertical mos transistor

Method of making mirror image memory cell transistor pairs featuring poly floating spacers

EEPROM with multi-member floating gate

Self-aligned non-volatile memory cell

Method for simultaneous fabrication of a nanocrystal and non-nanocrystal device

Method of making nonvolatile transistor pairs with shared control gate

Non-volatile memory array with simultaneous write and erase feature

Method for simultaneous fabrication of a nanocrystal and non-nanocrystal device

Multi-level memory cell array with lateral floating spacers

Non-thermally annealed doped semiconductor material and methods related thereto

Low voltage non-volatile memory cell with electrically transparent control gate

Contactless nonvolatile memory array

Ultrascalable vertical MOS transistor with planar contacts

CYPRESS SEMICONDUCTOR CORP

Fabrication sequence employing an oxide formed with minimized inducted charge and/or maximized breakdown voltage

MOTOROLA INC

Diffusing dopants into a semiconductor wafer

(unassigned)

Non-volatile semiconductor memory device