Charge trapping nanocrystal dielectric for non-volatile memory transistor

Abstract

A layer of nanocrystals for use in making EEPROMs is made by creating a matrix of silicon seeds in annealed silicon oxide atop a thin silicon dioxide layer. Then nanocrystals are grown on the seeds by vapor deposition of silane in a reactor until a time before agglomeration occurs as silicon atoms crystallize on the silicon seeds to form a layer of non-contacting nanocrystals. A protective insulative layer is then deposited over the nanocrystal layer.

1. Method of making a nanocrystal charge storage layer comprising:
 embedding silicon seeds in a silicon containing insulative layer, 
 etching the silicon containing insulative layer to expose the silicon seeds to an ambient environment, and 
 vapor depositing silicon onto the silicon seeds thereby growing silicon nanocrystals. 
 
     
     
       2. The method of  claim 1  wherein the silicon containing insulative layer is formed atop a layer of tunnel oxide. 
     
     
       3. The method of  claim 2  wherein said tunnel oxide layer is atop a silicon wafer substrate. 
     
     
       4. The method of  claim 1  further defined by depositing a protective layer over the silicon nanocrystals. 
     
     
       5. The method of  claim 1  further defined by stopping growth of silicon nanocrystals prior to agglomeration. 
     
     
       6. The method of  claim 1  wherein the silicon seeds are co-deposited with said silicon containing insulative layer. 
     
     
       7. Method of making a nanocrystal charge storage layer comprising:
 a) providing a planar silicon substrate portion, 
 b) depositing an insulating silicon dioxide layer over the planar substrate having a thickness in the range of 20–60 Angstroms, 
 c) depositing a silicon oxide compound layer over the insulating silicon dioxide layer having a thickness in the range of 20–50 Angstroms, 
 d) annealing the silicon oxide layer in an inert atmosphere until silicon nucleation seeds form at the silicon dioxide compound—silicon oxide boundary, 
 e) etching the silicon oxide layer to partially expose the silicon nucleation seeds, 
 f) vapor depositing silicon onto the silicon nucleation seeds wherein a layer of non-agglomerating nanocrystals is formed, 
 g) covering the layer of nanocrystals with a protective insulative layer. 
 
     
     
       8. The method of  claim 7  wherein the silicon oxide layer has a composition of Si x O y  where x is smaller than y. 
     
     
       9. The method of  claim 7  wherein the silicon oxide layer has a composition of Si x O y  where x is equal to y. 
     
     
       10. The method of  claim 7  wherein said annealing is by thermal annealing. 
     
     
       11. The method of  claim 7  wherein said annealing is by laser annealing. 
     
     
       12. The method of  claim 7  further defined by vapor depositing said silicon by introducing silane into a reactor. 
     
     
       13. The method of  claim 7  further defined by patterning the nanocrystal charge storage layer and forming non-volatile memory transistors. 
     
     
       14. Method of making a nanocrystal charge storage layer comprising:
 providing a doped bulk planar surface, with doping of the bulk to a degree adequate for building CMOS transistors, 
 depositing a silicon dioxide layer on said planar surface having a thickness less than 50 Angstroms as a first insulative layer, 
 depositing a second insulative layer atop the silicon dioxide layer, 
 depositing silicon seeds within said second insulative layer, 
 etching the second insulative layer to partially expose the silicon seeds, 
 growing silicon nanocrystals from the silicon seeds, and 
 covering the silicon nanocrystals with a third insulative layer. 
 
     
     
       15. The method of  claim 14  wherein the doped bulk is a doped silicon wafer. 
     
     
       16. The method of  claim 14  wherein said insulative layer is silicon oxide having the formula Si x O y , where x and y are integers. 
     
     
       17. The method of  claim 16  wherein y is greater than x. 
     
     
       18. The method of  claim 16  wherein y is equal to x. 
     
     
       19. The method of  claim 14  further defined by patterning the nanocrystal charge storage layer and forming non-volatile memory transistors. 
     
     
       20. The method of  claim 14  further defined by co-depositing said silicon seeds and said second insulative layer.