Inventor

CAPRIOLI PAUL

US88 patents

⚠️ This page may combine multiple inventors who share the name “CAPRIOLI PAUL”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

CAPRIOLI PAUL

SUN MICROSYSTEMS INC

Method and apparatus for reporting failure conditions during transactional execution

Circuitry and method for accessing an associative cache with parallel determination of data and data availability

Method and apparatus for supporting different modes of multi-threaded speculative execution

Generation of multiple checkpoints in a processor that supports speculative execution

Patchable and/or programmable pre-decode

Deferring loads and stores when a load buffer or store buffer fills during execute-ahead mode

Method and structure for pipelining of SIMD conditional moves

Arithmetic early bypass

Using a transactional execution mechanism to free up processor resources used by a busy-waiting thread

Method for graphically displaying hardware performance simulators

Method and apparatus for dynamically adjusting the aggressiveness of an execute-ahead processor to hide memory latency

Method and apparatus for enforcing membar instruction semantics in an execute-ahead processor

Selective execution of deferred instructions in a processor that supports speculative execution

Entering scout-mode when stores encountered during execute-ahead mode exceed the capacity of the store buffer

Patchable and/or programmable decode using predecode selection

Mechanism for eliminating the restart penalty when reissuing deferred instructions

Cache replacement policy to mitigate pollution in multicore processors

Method and structure for coordinating instruction execution in out-of-order processor execution using an instruction including an artificial register dependency

Branch target aware instruction prefetching technique

Method and apparatus for using multiple threads to spectulatively execute instructions

Mechanism for hardware tracking of return address after tail call elimination of return-type instruction

INTEL CORP

Systems, methods, and apparatuses for heterogeneous computing

Return-target restrictive return from procedure instructions, processors, methods, and systems

Systems, methods, and apparatuses for heterogeneous computing

Systems, methods, and apparatuses for heterogeneous computing

Technologies for shadow stack manipulation for binary translation systems

Technologies for translation cache management in binary translation systems

Custom protection against side channel attacks

Systems, methods, and apparatuses for heterogeneous computing

Accelerated interlane vector reduction instructions

Apparatuses, methods, and systems for swizzle operations in a configurable spatial accelerator

Detection of memory address aliasing and violations of data dependency relationships

CAPRIOLI PAUL

Method and apparatus for programmatically rewinding a register inside a transaction

Using address and non-address information for improved index generation for cache memories

Anti-prefetch instruction

System, apparatus, and method for transparent page level instruction translation

Index generation for cache memories

Method, apparatus, and system for efficiently handling multiple virtual address mappings during transactional execution canceling the transactional execution upon conflict between physical addresses of transactional accesses within the transactional execution

Instruction and logic to control transfer in a partial binary translation system

Hardware profiling mechanism to enable page level automatic binary translation

ORACLE AMERICA INC

Method and apparatus for improving transactional memory commit latency

Method and apparatus for synchronizing threads on a processor that supports transactional memory

Return address stack recovery in a speculative execution computing apparatus

Method and apparatus for selectively prefetching based on resource availability

Pseudo-LRU cache line replacement for a high-speed cache

Method and apparatus for measuring performance during speculative execution

Method and apparatus for counting instructions during speculative execution

KANHERE ABHAY S

Instruction and logic to perform dynamic binary translation

AL-OTOOM MUAWYA M

Memory disambiguation hardware to support software binary translation

DroneTerminus LLC

Package acceptance, guidance, and refuel system for drone technology